Results 191 to 200 of about 10,650 (234)
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IEEE Transactions on Instrumentation and Measurement, 2021
This article proposes and validates a low complexity multichannel ring-oscillator (RO)-based time-to-digital converter (TDC) architecture for field-programmable gate arrays (FPGAs).
Safa Berrima, Y. Blaquière, Y. Savaria
semanticscholar +1 more source
This article proposes and validates a low complexity multichannel ring-oscillator (RO)-based time-to-digital converter (TDC) architecture for field-programmable gate arrays (FPGAs).
Safa Berrima, Y. Blaquière, Y. Savaria
semanticscholar +1 more source
A compact Time-to-Digital Converter (TDC) module with 10 ps resolution and less than 1.5% LSB DNL
IEEE Photonics Conference 2012, 2012We present a low-power Time-to-Digital Converter (TDC) module that provides 10 ps timing resolution, DNL better than 1.5% LSB and 160 ns dynamic range within a compact 6 cm × 6 cm × 8 cm housing. The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via ...
MARKOVIC, BOJAN +8 more
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A Two-Stage Interpolation Time-to-Digital Converter Implemented in 20 and 28 nm FGPAs
IEEE transactions on industrial electronics (1982. Print)This article presents a two-stage interpolation time-to-digital converter (TDC), combining a Vernier gray code oscillator TDC (VGCO-TDC) and a tapped-delay line TDC (TDL-TDC).
Yu Wang +4 more
semanticscholar +1 more source
IEEE Journal of Solid-State Circuits, 2019
A phenomenon called parallel-output misalignment (POM), which intrinsically occurs in ring-type time-to-digital converters (TDCs) like gated-ring oscillator (GRO) or Vernier-ring TDCs, is discussed in this paper. We found that the phase noise caused by POM error may be larger than that due to quantization error by up to 22 dB or even more.
Tuoxin Wang +2 more
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A phenomenon called parallel-output misalignment (POM), which intrinsically occurs in ring-type time-to-digital converters (TDCs) like gated-ring oscillator (GRO) or Vernier-ring TDCs, is discussed in this paper. We found that the phase noise caused by POM error may be larger than that due to quantization error by up to 22 dB or even more.
Tuoxin Wang +2 more
openaire +1 more source
IEEE Transactions on Nuclear Science, 2019
In a field-programmable gate array (FPGA)-based time-to-digital converter (TDC), the hit signal to be measured launches out a segment of the clock-like signal propagating along the tapped delay line (TDL).
Yonggang Wang +4 more
semanticscholar +1 more source
In a field-programmable gate array (FPGA)-based time-to-digital converter (TDC), the hit signal to be measured launches out a segment of the clock-like signal propagating along the tapped delay line (TDL).
Yonggang Wang +4 more
semanticscholar +1 more source
Wireless Personal Communications, 2018
Phase locked loops (PLLs) are utilized as a part of clock recovery and frequency synthesis. Entirely digital PLLs are more reasonable for the solid execution with different circuits contrasted with the customary usage of the PLLs. The all-digital PLLs are additionally autonomous of process varieties and can be efficiently ported to various innovations.
T. M. Sathish Kumar, P. S. Periasamy
openaire +1 more source
Phase locked loops (PLLs) are utilized as a part of clock recovery and frequency synthesis. Entirely digital PLLs are more reasonable for the solid execution with different circuits contrasted with the customary usage of the PLLs. The all-digital PLLs are additionally autonomous of process varieties and can be efficiently ported to various innovations.
T. M. Sathish Kumar, P. S. Periasamy
openaire +1 more source
Time-Interpolated Vernier Digital-to-Time Converter with Applications in Time-Mode SAR TDC
2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 2023Daniel Junehee Lee, Fei Yuan, Yushi Zhou
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A Cyclic Vernier Digital-to-Time Converter for Time-Mode Successive Approximation TDC
2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), 2023Daniel Junehee Lee, Fei Yuan, Yushi Zhou
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Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI), 2022Rodrigo N. Wuerdig +3 more
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