Results 41 to 50 of about 10,650 (234)

Design of a 3 GHz fine resolution LC DCO [PDF]

, 2017
In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning.
Zhao, Xuming, active 21st century
core   +1 more source

Time-to-Digital Converter IP-Core for FPGA at State of the Art

IEEE Access, 2021
The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time–Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices, such as FPGAs,
F. Garzetti, N. Corna, N. Lusardi, A. Geraci   +3 more
semanticscholar   +1 more source

A Coarse-Fine Time-to-Digital Converter

ITM Web of Conferences, 2017
A design of time-to-digital converter (TDC) using a coarse-fine conversion scheme is presented. The coarse stage was accomplished by a delay line, and used a loop counter at the end of the delay line to achieve wide dynamic range. The fine stage utilized
Chen Ya-Qian, Meng Li-Ya, Lin Xiao-Gang
doaj   +1 more source

Bio-inspired 0.35μm CMOS Time-to-Digital Converter with 29.3ps LSB [PDF]

, 2006
Time-to-digital converter (TDC) integrated circuit is introduced in this paper. It is based on chain of delay elements composing a regular scalable structure. The scheme is analogous to the sound direction sensitivity nerve system found in barn owl.
Chung, Jen-Feng, Mozsary, Andras, Rodríguez Vázquez, Ángel Benito, Roska, Tamás   +3 more
core   +1 more source

Multi-Channel FPGA Time-to-Digital Converter With 10 ps Bin and 40 ps FWHM

IEEE Transactions on Instrumentation and Measurement, 2022
We present a novel architecture for multi-channel time-to-digital converters (TDCs) to be implemented into low-cost field-programmable gate arrays (FPGAs), achieving 10-ps least significant bit (LSB), 164- $\mu \text{s}$ full-scale range, and good ...
D. Portaluppi, K. Pasquinelli, I. Cusini, F. Zappa   +3 more
semanticscholar   +1 more source

Design and Analysis of a Multirate 5-bit High-Order 52 fs_rms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA

IEEE Access, 2021
This paper describes FPGA implementation of a high-order continuous-time multi-stage noise-shaping (MASH) $\Delta \Sigma $ time-to-digital converter (TDC).
Ahmad Mouri Zadeh Khaki, Ebrahim Farshidi, Karim Ansari Asl, Sawal Hamid Md Ali, Masuri Othman   +4 more
doaj   +1 more source

All-digital self-adaptive PVTA variation aware clock generation system for DFS [PDF]

, 2014
An all-digital self-adaptive clock generation system capable of adapt the clock frequency to compensate the effects of PVTA variations on the IC propagation delay and satisfy an externally set propagation length condition is presented.
Calomarde Palomino, Antonio, Moll Echeto, Francisco de Borja, Pérez Puigdemont, Jordi   +2 more
core   +1 more source

A search for massive neutral bosons in orthopositronium decay [PDF]

, 1995
We have searched for an exotic decay of orthopositronium into a single photon and a short-lived neutral boson in the hitherto unexplored mass region above 900 ${\rm keV}/{\it c}^{2}$, by noting that this decay is one of few remaining candidates which ...
Adkins, Adkins, Adkins, Adkins, Akopyan, Asai, Asai, Asai, Atoyan, Caswell, Chang, Gidley, Hyodo, J. Kataoka, K. Shigekuni, M. Fujikawa, Marko, Mitsui, Nico, Orito, S. Orito, T. Maeno, Tsuchiaki, Westbrook, Westbrook, Y. Nishihara, Y. Watanabe   +26 more
core   +2 more sources

An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

Journal of Electrical and Computer Engineering, 2014
We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL).
Chao Chen, Shengwei Meng, Zhenghuan Xia, Guangyou Fang, Hejun Yin   +4 more
doaj   +1 more source

A 19 ps Precision and 170 M Samples/s Time-to-Digital Converter Implemented in FPGA with Online Calibration

Applied Sciences, 2022
This paper presents a 19 ps precision and 170 M samples/s time-to-digital converter (TDC) in FPGA. Through the direct count method and tapped delay line method, the coarse count and fine count can be extracted, respectively.
Mengdi Zhang, Ye Zhao, Zhengsheng Han, F. Zhao   +3 more
semanticscholar   +1 more source