Results 11 to 20 of about 1,137 (197)
IEEE Journal of the Electron Devices Society, 2020 Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to
Hisashi Kino +2 more
doaj +1 more source
Analysis on Tunnel Field-Effect Transistor with Asymmetric Spacer
Applied Sciences, 2020 Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously.
Hyun Woo Kim, Daewoong Kwon
doaj +1 more source
Steep Switching Characteristics of L-Shaped Tunnel FET With Doping Engineering
IEEE Journal of the Electron Devices Society, 2021 In this work, a L-shaped tunnel FET (TFET), which has the dominant tunneling current in the normal direction to the gate, is introduced with the doping engineering and its electrical characteristics are analyzed using TCAD device simulations.
Hyun Woo Kim, Daewoong Kwon
doaj +1 more source
Opportunties and challenges of tunnel FETs
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016 Sustaining of Moore's Law over the next decade will require not only continued scaling of the physical dimensions of transistors but also performance improvement and aggressive reduction in power consumption. Hetero-junction Tunnel FET (TFET) have emerged as promising transistor candidates for supply voltage scaling down to sub-0.5V due to the ...
Rahul Pandey +2 more
openaire +1 more source
Advances in steep-slope tunnel FETs [PDF]
2016 46th European Solid-State Device Research Conference (ESSDERC), 2016 Tunnel FETs (TFETs) with steep subthreshold slope have been attracting much attention as building blocks for future low-power integrated circuits and CMOS technology devices. Here we report on recent advances in vertical TFETs using III–V/Si heterojunctions.
Katsuhiro Tomioka +2 more
openaire +1 more source
1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design
IEEE Journal of the Electron Devices Society, 2015 In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On ...
Arnab Biswas, Adrian M. Ionescu
doaj +1 more source
Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET
IEEE Access, 2022 We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation.
Abdullah Al Mamun Mazumder +3 more
doaj +1 more source
Tunnel FET Analog Benchmarking and Circuit Design
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2018 A platform for benchmarking tunnel field-effect transistors (TFETs) for analog applications is presented and used to compare selected TFETs to FinFET technology at the 14-nm node.
Hao Lu +5 more
doaj +1 more source
Variable-Barrier Quantum Coulomb Blockade Effect in Nanoscale Transistors
Nanomaterials, 2022 Current–voltage characteristics of a quantum dot in double-barrier configuration, as formed in the nanoscale channel of silicon transistors, were analyzed both experimentally and theoretically.
Pooja Yadav +3 more
doaj +1 more source
Steep switching in trimmed-gate tunnel FET
AIP Advances, 2018 We propose a tunnel field-effect transistor (TFET) having a trimmed gate (TG) structure, which considerably improves the subthreshold swing (SS). The TG structure truncates the needless long band-to-band tunneling (BTBT) paths to a “channel”, which ...
Hidehiro Asai +5 more
doaj +1 more source