Results 11 to 20 of about 1,083 (193)
A Novel Tunnel Oxide Based Tunnel FET
ECS Transactions, 2011 In this work, we propose a novel tunnel oxide based Tunnel FET. This novel Tunnel FET can achieve high drive currents, low SS, low off currents and many other superb device characteristics.
Zhijiong Luo +5 more
core +2 more sources
Novel UHF passive rectifier with tunnel FET devices [PDF]
2015 IEEE Computer Society Annual Symposium on VLSI, 2015 The increase of the losses in UHF passive rectifiers with Tunnel FET devices at large RF AC amplitudes are mainly due to the high reverse current inherent of this technology when subjected to high reverse bias conditions.
Nunes Cavalheiro, David Manuel +2 more
core +3 more sources
Innovative tunnel FET architectures
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2018 session 3: SimulationInternational audienceWe propose three innovative SOI Tunnel FET architectures. They are evaluated and compared with a standard TFET structure using Sentaurus TCAD.
Vinet, Maud +15 more
core +2 more sources
Study of a fringing field biosensor tunnel-FET
ECS Journal of Solid State Science and Technology, 2021 In this paper, we present a comprehensive study of the Fringing Field Biosensor Tunnel-FET (Bio-TFET) device based on 2Ddevice simulation. The presence of a biomaterial with a distinct dielectric constant (k, where ∈ = k∗∈0) on the underlap region (LUD ...
Agopian, P. G.D. [UNESP] +2 more
core +4 more sources
A tunnel-FET device model based on Verilog-A applied to circuit simulation
2015 IEEE International Electron Devices Meeting (IEDM), 2018 This work proposes a simple methodology for using Tunnel-FET devices, which do not have any accurate first order analytic models, for allowing the integrated circuit simulation with these devices.
Rangel, R. S. +2 more
core +3 more sources
Advances in steep-slope tunnel FETs [PDF]
2016 46th European Solid-State Device Research Conference (ESSDERC), 2016 Tunnel FETs (TFETs) with steep subthreshold slope have been attracting much attention as building blocks for future low-power integrated circuits and CMOS technology devices. Here we report on recent advances in vertical TFETs using III–V/Si heterojunctions.
Katsuhiro Tomioka +2 more
openaire +1 more source
Opportunties and challenges of tunnel FETs
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016 Sustaining of Moore's Law over the next decade will require not only continued scaling of the physical dimensions of transistors but also performance improvement and aggressive reduction in power consumption. Hetero-junction Tunnel FET (TFET) have emerged as promising transistor candidates for supply voltage scaling down to sub-0.5V due to the ...
Rahul Pandey +2 more
openaire +1 more source
Tunnel FET Analog Benchmarking and Circuit Design
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2018 A platform for benchmarking tunnel field-effect transistors (TFETs) for analog applications is presented and used to compare selected TFETs to FinFET technology at the 14-nm node.
Hao Lu +5 more
doaj +1 more source
Variable-Barrier Quantum Coulomb Blockade Effect in Nanoscale Transistors
Nanomaterials, 2022 Current–voltage characteristics of a quantum dot in double-barrier configuration, as formed in the nanoscale channel of silicon transistors, were analyzed both experimentally and theoretically.
Pooja Yadav +3 more
doaj +1 more source
Steep switching in trimmed-gate tunnel FET
AIP Advances, 2018 We propose a tunnel field-effect transistor (TFET) having a trimmed gate (TG) structure, which considerably improves the subthreshold swing (SS). The TG structure truncates the needless long band-to-band tunneling (BTBT) paths to a “channel”, which ...
Hidehiro Asai +5 more
doaj +1 more source