Results 81 to 90 of about 1,083 (193)

Gate Field Plate Structure for Subthreshold Swing Improvement of Si Line-Tunneling FETs

IEEE Access, 2019
Tunnel field-effect transistors (TFETs) are promising for use in ultralow-power applications owing to their distinct band-to-band tunneling operation.
Xiangzhan Wang, Zhouquan Tang, Lei Cao, Jingchun Li, Yang Liu   +4 more
doaj   +1 more source

Silicon tunnel FET with average subthreshold slope of 55 mV/dec at low drain currents

, 2017
In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. The fabricated device shows an on-current of Ion = 2.55 × 10−7 A/µm at Vds = Von = Vgs − Voff = −0.5 V for an Ioff = 1 nA/µm and an average ...
S. Glass, von den Driesch, N., Zhao, Q. T., Bernardy, P., Narimani, K., S. Mantl, Mantl, S., K. Narimani, Rieger, T., Q.T. Zhao, Glass, S., N. von den Driesch, P. Bernardy, T. Rieger   +13 more
core   +1 more source

Silicon Nitride Resistive Memories

Advanced Electronic Materials, EarlyView.
Amorphous SiNx is an attractive resistance switching material for ReRAM applications due to its physicochemical properties, such as humidity resistance, low oxygen diffusivity, and is used as a metal diffusion blocker. By modifying the ratio between N and Si atoms, the microstructure of the SiNx is affected, rendering it possible to change the ...
Alexandros‐Eleftherios Mavropoulis, Nikolaos Vasileiadis, Iosif‐Angelos Fyrigos, Emmanouil Stavroulakis, Caroline Bonafos, Pascal Normand, Georgios Ch. Sirakoulis, Panagiotis Dimitrakis   +7 more
wiley   +1 more source

Performance Projections for a Reconfigurable Tunnel NanoFET

IEEE Journal of the Electron Devices Society, 2017
Theoretical performance projections of a reconfigurable tunnel (RT) field-effect transistor (FET) employing multiple parallel 1-D channels are given. The RT-nanoFET can be reconfigured on demand from pto n-type and from low power (LP) to high performance
Stefan Blawid, Denise L. M. de Andrade, Sven Mothes, Martin Claus   +3 more
doaj   +1 more source

Source doping profile design for Si and Ge tunnel FET

, 2014
The source junction doping profile design for Si and Ge tunnel FET (TFET) is discussed and compared in this paper. By using Sentaurus TCAD tools with calibrated dynamic non-local band-to-band tunneling and non-local trap-assisted-tunneling models, it is ...
Chen, Shaowen, Huang, Qianqian, Huang, Ru   +2 more
core   +1 more source

Efficient In‐Hardware Matrix–Vector Multiplication and Addition Exploiting Bilinearity of Schottky Barrier Transistors Processed on Industrial FDSOI

Advanced Electronic Materials, EarlyView.
ABSTRACT Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In‐hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency.
Juan P. Martinez, Niladri Bhattacharjee, Yuxuan He, Giulio Galderisi, Brojogopal Sapui, Sara Mannaa, Ian O'Connor, Violetta Sessi, Peter Javorka, Thomas Mikolajick, Jens Trommer   +10 more
wiley   +1 more source

Comparative Analysis of Carrier Statistics on MOSFET and Tunneling FET Characteristics

IEEE Journal of the Electron Devices Society, 2015
This paper presents a comparison analysis of carrier statistics on numerical simulations of MOSFET and tunneling FET (TFET). While the MOSFET current characteristics are not sensitive to the carrier statistic utilized in the simulation, a detailed ...
Dan Li, Baili Zhang, Haijun Lou, Lining Zhang, Xinnan Lin, Mansun Chan   +5 more
doaj   +1 more source

Toward Capacitive In‐Memory‐Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware

Advanced Intelligent Discovery, EarlyView.
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj, Ella Paasio, Sayani Majumdar   +2 more
wiley   +1 more source

Single Grain Boundary Dopingless PNPN Tunnel FET on Recrystallized Polysilicon: Proposal and Theoretical Analysis

IEEE Journal of the Electron Devices Society, 2015
A single grain boundary dopingless PNPN tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is studied by varying the position of the grain boundary in the channel.
Mamidala Saketh Ram, Dawit Burusie Abdi
doaj   +1 more source

Quantum mechanical analysis of 2D transition metal dichalcogenide material based vertical heterojunction tunnel FET

AIP Advances, 2020
In this work, a single layer n-doped MoS2 and p-doped WTe2 based vertical heterojunction tunnel FET has been investigated through a well-organized quantum mechanical approach.
Tanmoy Kumar Paul, Quazi Deen Mohd Khosru   +1 more
doaj   +1 more source