Results 81 to 90 of about 317,981 (244)
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj +2 more
wiley +1 more source
Comparative Study of Steep Switching Devices for 1T Dynamic Memory
This work focuses on understanding the operation and performance of various steep switching devices (subthreshold slope sub 60 mV/decade), namely Thin-Capacitively Coupled Thyristor (TCCT), Field Effect Diode (FED), Zero sub-threshold swing and Zero ...
Nupur Navlakha +3 more
doaj +1 more source
Comparative Analysis of Carrier Statistics on MOSFET and Tunneling FET Characteristics
This paper presents a comparison analysis of carrier statistics on numerical simulations of MOSFET and tunneling FET (TFET). While the MOSFET current characteristics are not sensitive to the carrier statistic utilized in the simulation, a detailed ...
Dan Li +5 more
doaj +1 more source
This article outlines how artificial intelligence could reshape the design of next‐generation transistors as traditional scaling reaches its limits. It discusses emerging roles of machine learning across materials selection, device modeling, and fabrication processes, and highlights hierarchical reinforcement learning as a promising framework for ...
Shoubhanik Nath +4 more
wiley +1 more source
Performance Projections for a Reconfigurable Tunnel NanoFET
Theoretical performance projections of a reconfigurable tunnel (RT) field-effect transistor (FET) employing multiple parallel 1-D channels are given. The RT-nanoFET can be reconfigured on demand from pto n-type and from low power (LP) to high performance
Stefan Blawid +3 more
doaj +1 more source
Parametric Analysis of Spiking Neurons in 16 nm Fin Field‐Effect Transistor Technology
Energy efficient computing has driven a shift toward brain‐inspired neuromorphic hardware. This study explores the design of three distinct silicon neuron topologies implemented in 16 nm fin field‐Effect transistor technology. While the Axon‐Hillock design achieves gigahertz throughput, its functional fragility persists. The Morris–Lecar model captures
Logan Larsh +3 more
wiley +1 more source
A single grain boundary dopingless PNPN tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is studied by varying the position of the grain boundary in the channel.
Mamidala Saketh Ram, Dawit Burusie Abdi
doaj +1 more source
In this work, a single layer n-doped MoS2 and p-doped WTe2 based vertical heterojunction tunnel FET has been investigated through a well-organized quantum mechanical approach.
Tanmoy Kumar Paul +1 more
doaj +1 more source
Exploiting Ferroelectric and Spintronic Dynamics for Neural Network Computation
Ferroelectric and spintronic devices, relying on the control of polarization and magnetization, offer intrinsically fast, durable, energy‐efficient, and low‐latency building blocks for analog in‐memory computing. The hysteretic dynamics of an order parameter are leveraged to provide nonvolatile, multistate memory and nonlinear switching. Brain‐inspired
Dashiell Harrison +4 more
wiley +1 more source
Hand and wrist configurations in patients with Carpal Tunnel Syndrome [PDF]
The association between hand and wrist configurations was investigated in this study. The hand and wrist dimensions of sixty patients with carpal tunnel syndrome and sixty healthy control subjects were measured using specific anatomical landmarks.
Gatt, Ray +2 more
core

