Results 141 to 150 of about 1,247 (195)

Work-Function Variation Effects of Tunneling Field-Effect Transistors (TFETs)

IEEE Electron Device Letters, 2013
The work-function variation (WFV) effects of tunneling field-effect transistors (TFETs) are discussed for the first time. According to the 3-D device simulation results, TFETs are less immune to the WFV than metal-oxide-semiconductor FETs (MOSFETs) in terms of subthreshold swing (S) and threshold voltage (Vth).
Kyoung Min Choi, Woo Young Choi
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Characterization of Charge Plasma-based Junctionless Tunneling Field Effect Transistor (JL-TFET)

2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2020
The steep doping profile associated with conventional Tunneling Field Effect Transistor (TFET) provides significant hindrances from a fabrication perspective despite the obvious merits of the device. Junctionless TFET (JL-TFET) alleviates the problem considerably by introducing a uniform doping profile across the device.
Nafis Mustakim, Sazzad Hussain, Jibesh K. Saha   +2 more
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Gate-Normal Negative Capacitance Tunnel Field-Effect Transistor (TFET) With Channel Doping Engineering

IEEE Transactions on Nanotechnology, 2021
In this work, a negative capacitance tunnel FET (NCTFET) with the tunneling current in the normal direction to the gate is proposed with channel doping engineering and its electrical characteristics are investigated using TCAD simulations with calibrated model parameters.
Hyun Woo Kim, Daewoong Kwon
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Impact of mask alignment on the tunneling field effect transistor (TFET)

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005., 2005
The tunneling field effect transistor (TFET) is a standard CMOS process flow compatible device which shows improved short channel characteristics and lower static power consumption. The device is generated by the p-implant layer overlapping the source extension.
T. Nirschl, U. Schaper, J. Einfeld, S. Henzler, M. Sterkel, J. Singer, M. Fulde, W. Hansch, G. Georgakos, D. Schmitt-Landsiedell   +9 more
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Scaling properties of the tunneling field effect transistor (TFET): Device and circuit

Solid-State Electronics, 2006
Abstract The scaling properties of the tunneling field effect transistor (TFET) are shown using standard 130 nm, 90 nm, and 65 nm CMOS process flows. For the different technology nodes the temperature dependence is presented. The device characteristic does not show degradation after a combined voltage and temperature cycle.
Th. Nirschl, St. Henzler, J. Fischer, M. Fulde, A. Bargagli-Stoffi, M. Sterkel, J. Sedlmeir, C. Weber, R. Heinrich, U. Schaper, J. Einfeld, R. Neubert, U. Feldmann, K. Stahrenberg, E. Ruderer, G. Georgakos, A. Huber, R. Kakoschke, W. Hansch, D. Schmitt-Landsiedel   +19 more
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Temperature Influence on Tunnel Field Effect Transistors (TFETs) with Low Ambipolar Currents

ECS Transactions, 2011
This work presents a study of the temperature impact on tunnel field effect transistors performance. After design considerations regarding undesirable ambipolar currents, TFETs were simulated for temperatures ranging from 100 to 400 K. Bearing this objective in mind, the influence of each one of the most relevant transport mechanisms was analyzed and ...
Marcio D. Martino, Paula G. Der Agopian, Sebastião G. Dos Santos Filho, João A. Martino   +3 more
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Two-Dimensional Potential-Based Model for Tunnel Field-Effect Transistor (TFET)

2020
In this paper, we propose a two-dimensional analytical model of silicon-on-insulator tunneling field-effect transistors (SOI TFETs) by applying the superposition principle. By solving 2D Poisson’s equation with the help of boundary conditions of channel region and gate oxide region, we calculated the surface potential and electric field for both ...
Netravathi Kulkarni, P. Vimala
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Low voltage tunnel field-effect transistor (TFET) and method of making same

2023
A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region
Seabaugh, Alan C., Zhou, Guangle, Xing, Huili (Grace), Wistey, Mark A., Fay, Patrick, Koswatta, Siyuranga, Lu, Yeqing   +6 more
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Design of Gate Engineered Heterojunction Surrounding Gate Tunnel Field Effect Transistor (HSG TFET)

2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE), 2020
This paper presents, the design architecture of the Heterojunction Surrounding Gate (HSG) Tunnel Field Effect Transistor (TFET) employing Single Material (SM) gate and Dual Material (DM) gate with two different work function is proposed. A concise comparison between DM HSG TFET, SM HSG TFET and conventional Silicon Surrounding Gate (SG) TFET is ...
G Navya Shree, U Priyadarshini, M Keerthana, P. Vimala   +3 more
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The 1T photo pixel cell using the tunneling field effect transistor (TFET)

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005., 2005
The tunneling field effect transistor (TFET) is a quantum-mechanical device which is able to extend the epoch of the standard CMOS process by offering reduced short channel effects and smaller leakage currents. First, the mode of operation of the TFET is presented. Next, the application as photo pixel cell is proposed comprising only one device.
T. Nirschl, A. Bargagli-Stoffi, J. Fischer, S. Henzler, null Peng-Fei Wang, M. Sterkel, W. Hansch, D. Schmitt-Landsiedel   +7 more
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