Results 121 to 130 of about 10,230,919 (179)
Screen printed logic circuit for configurable high‐density EMG electrodes. The multilayer electrode kernel combines eight OECT‐based transmission channels with an integrated OECT‐based 3–8 decoder circuit to activate a single channel while blocking the rest.
Luis Pelaez Murciego +6 more
wiley +1 more source
Demonstration of Vertically Stacked ZnO/Te Complementary Field‐Effect Transistor
The complementary field‐effect transistor (CFET) structure is a highly area‐efficient technology. However, their fabrication entails highly complex integration processes using wafer transfer or recrystallization, which has been limiting further ...
Kiyung Kim +8 more
doaj +1 more source
Boolean AND Gate Made from NAND Gates
A Boolean AND gate composed of only NAND gates in LabVIEW.
steve koch (97772) +4 more
core +1 more source
Discrete-Trap Effects on 3-D NAND Variability – Part I: Threshold Voltage
In this two-part article we discuss the difference between a continuous and a discrete approach to trap modeling in the simulation of 3-D NAND Flash memories with polysilicon channel. In Part I we focus on threshold voltage $({\mathrm { V}}_{\mathrm { T}
Gerardo Malavena +9 more
doaj +1 more source
Sub-1V, flexible, all-polymer complementary logic circuits based on electrolyte-gated transistors
Electrolyte-gated transistors (EGTs) are typically limited to p-type operation, with stable n-type devices remaining scarce. In this study, we demonstrate high-performance n-type EGTs using a poly(benzimidazobenzophenanthroline) (BBL) polymer ...
Su Jung Kim +7 more
doaj +1 more source
Wafer‐Scale Bi2O2Se‐on‐Insulator Thin Films for Integrated Electronics
Quasi‐2D semiconducting Bi2O2Se has emerged as a promising candidate for beyond‐silicon electronics due to its outstanding transport performances. However, large‐area growth of high‐quality Bi2O2Se films, which is a critical prerequisite for batch ...
Xi Chen +4 more
doaj +1 more source
A NOR Emulation Strategy over NAND Flash Memory
快閃記憶體大致可分為兩類:NOR型快閃記憶體及NAND型快閃記憶體。一般而言,因為有就地執行(eXecute-In-Place,XIP)和快速讀取等特性,NOR型快閃記憶體應用上適用於儲存程式的可執行檔。而擁有較大容量與較快寫入速度的NAND型快閃記憶體則適用於資料儲存。此外,兩者在成本上有很大的差距,NOR型快閃記憶體相對於NAND型快閃記憶體高出許多。基於市場的趨勢,若能以較具經濟效益的NAND型快閃記憶體取代NOR型快閃,將可大幅地降低成本、提升毛利。在這篇論文中 ...
Lin, Chien-Hung, 林建宏
core
NAND flash memory technologies
This book discusses basic and advanced NAND flash memory technologies, including the principle of NAND flash, memory cell technologies, multi-bits cell technologies, scaling challenges of memory cell, reliability, and 3-dimensional cell as the future ...
Aritome, Seiichi
core
7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers
Today's explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to planar NAND and is quickly displacing planar NAND in the SSD market, due to its performance, reliability ...
Dongku Kang +29 more
core +5 more sources
Effect of Device Scaling on Lateral Migration Mechanism of Electrons in V-NAND
In this paper, we analyzed lateral migration (LM) mechanism of V-NAND occurring during retention operation depending on scaling of geometric parameters using TCAD simulation. Modeling for LM was performed and the behavior of time-constant (τ) parameter used for modeling was analyzed.
Changbeom Woo +3 more
openaire +2 more sources

