Channel Modeling and Quantization Design for 3D NAND Flash Memory [PDF]
Entropy, 2023 As the technology scales down, two-dimensional (2D) NAND flash memory has reached its bottleneck. Three-dimensional (3D) NAND flash memory was proposed to further increase the storage capacity by vertically stacking multiple layers.
Cheng Wang +5 more
doaj +4 more sources
Random Telegraph Noise in 3D NAND Flash Memories. [PDF]
Micromachines (Basel), 2021 In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport.
Spinelli AS +3 more
europepmc +5 more sources
Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory [PDF]
Micromachines, 2021 In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better ...
Woo-Jin Jung, Jun-Young Park
doaj +2 more sources
3D NAND Flash Memory Based on Double-Layer NC-Si Floating Gate with High Density of Multilevel Storage [PDF]
Nanomaterials, 2022 As a strong candidate for computing in memory, 3D NAND flash memory has attracted great attention due to the high computing efficiency, which outperforms the conventional von-Neumann architecture. To ensure 3D NAND flash memory is truly integrated in the
Xinyue Yu +6 more
doaj +2 more sources
Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash [PDF]
Micromachines, 2023 The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang +4 more
doaj +2 more sources
Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages [PDF]
Micromachines, 2022 Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated.
Dongwoo Lee, Changhwan Shin
doaj +2 more sources
Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories [PDF]
Micromachines, 2021 Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories.
Fei Chen +6 more
doaj +2 more sources
Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors [PDF]
Sensors, 2023 Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling,
Hanshui Fan +6 more
doaj +2 more sources
Recent Progress on 3D NAND Flash Technologies [PDF]
Electronics (Switzerland), 2021 Since 3D NAND was introduced to the industry with 24 layers, the areal density has been successfully increased more than ten times, and has exceeded 10 Gb/mm2 with 176 layers. The physical scaling of XYZ dimensions including layer stacking and footprint scaling enabled the density scaling. Logical scaling has been successfully realized, too.
Akira Goda
exaly +2 more sources
A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory [PDF]
Micromachines, 2023 With gate length (Lg) and gate spacing length (Ls) shrinkage, the cell-to-cell z-interference phenomenon is increasingly severe in 3D NAND charge-trap memory. It has become one of the key reliability concerns for 3D NAND cell scaling.
Jianquan Jia +3 more
doaj +2 more sources