Results 91 to 100 of about 1,500,059 (236)

A Fully Integrated Analog Processing‐in‐Memory System Based on Charge‐Trap Flash Synapse Arrays and Successive Integration‐and‐Rescaling Neurons

open access: yesAdvanced Intelligent Systems, EarlyView.
A fully integrated analog processing‐in‐memory system is demonstrated, combining charge‐trap flash synapse arrays with a successive integration‐and‐rescaling neuron circuit. The architecture performs bit‐sliced analog accumulation with high linearity and low power, achieving efficient and scalable analog in‐memory computing and bridging device‐level ...
Sojoong Kim   +4 more
wiley   +1 more source

An unusual titanosaur axis from the Upper Cretaceous of Brazil and its significance for sauropod anatomy and systematics

open access: yesThe Anatomical Record, EarlyView.
Abstract The Upper Cretaceous São José do Rio Preto Formation (Bauru Group, southeastern Brazil) has yielded a fragmentary but taxonomically diverse record of titanosaur sauropods, although elements from cervical series remain scarce. Here, we describe a nearly complete sauropod axis from the Vila Ventura Paleontological Area, representing an uncommon ...
Bruno A. Navarro   +7 more
wiley   +1 more source

Keggin‐Type Aluminum Polyoxometalate‐Mediated Oxidation of Amorphous Carbon for Engineered Electrochemical Interfaces

open access: yesCarbon Energy, EarlyView.
Keggin‐type Al‐POM‐coated silica achieves selective surface oxidation of amorphous carbon through electrostatic attraction and proton‐coupled oxidation, tailoring interfacial properties for lithium‐ion batteries and semiconductor processes. ABSTRACT Amorphous carbon is widely used in energy storage and semiconductor technologies, where surface ...
Ganggyu Lee   +13 more
wiley   +1 more source

Computational design of two‐dimensional MA2Z4 family field‐effect transistor for future Ångström‐scale CMOS technology nodes

open access: yesInfoMat, EarlyView.
Two‐dimensional MA2Z4 such as MoSi2N4 offer a new path to extend transistor scaling beyond the limits of silicon. Due to their exceptional properties, these 2D semiconductors are promising candidates for future Ångström‐scale CMOS technology. This review outlines the computational design and roadmap bridging materials discovery, device design and ...
Che Chen Tho   +11 more
wiley   +1 more source

Thin Fluoride Insulators for Improved 2D Transistors: From Deposition Methods to Recent Applications

open access: yesphysica status solidi (RRL) – Rapid Research Letters, EarlyView.
2D materials hold significant promise for next‐generation electronic and optoelectronic devices, but suitable gate dielectrics are still a challenge. Fluoride insulators, offering inert, dangling‐bond‐free surfaces, have recently emerged as strong candidates. This review covers recent publications on high‐quality fluoride thin‐film deposition and their
Behzad Dadashnia   +3 more
wiley   +1 more source

A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory

open access: yesMicromachines
The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction
Kaikai You   +3 more
doaj   +1 more source

Complementary Logic Driven by Dielectrophoretic Assembly of 2D Semiconductors

open access: yesAdvanced Functional Materials, Volume 36, Issue 11, 5 February 2026.
Scalable, parallel fabrication of complementary logic gates is demonstrated using electric‐field‐driven deterministic assembly of electrochemically exfoliated 2D n‐type MoS2 and p‐type WSe2 nanosheets. This strategy yields MoS2 and WSe2 transistors featuring average mobilities of 4.3 and 3.0 cm2 V−1 s−1, respectively, and on/off ratios of > 104 ...
Dongjoon Rhee   +10 more
wiley   +1 more source

Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory

open access: yesElectronics
This paper presents an innovative approach to alleviate Z-interference in 3D NAND flash memory by proposing an optimized confined nitride trap layer structure.
Yeeun Kim, S. Hong, Jong Kyung Park
semanticscholar   +1 more source

Vertical Self‐Rectifying Memristive Arrays for Page‐Wise Parallel Logic and Arithmetic Processing

open access: yesAdvanced Materials, Volume 38, Issue 8, 6 February 2026.
This study proposes a page‐wise logic‐in‐memory architecture realized in a 3D vertical resistvie random‐access memory array of self‐rectifying memristors. By introducing intra‐ and inter‐page logic primitives, the system enables Boolean and arithmetic operations to be executed directly within the memory.
Kunhee Son   +12 more
wiley   +1 more source

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