Results 71 to 80 of about 2,082 (171)

White Light Interference Solution for Novel 3D NAND VIA Dishing Metrology

Journal of Microelectronic Manufacturing, 2019
In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher, peripheral circuits may account for more than 50% of ...
Xiaoye Ding, Sicong Wang, Yi Zhou, Yanzhong Ma, Le Yang, Chi Chen   +5 more
doaj   +1 more source

Investigation of the Connection Schemes between Decks in 3D NAND Flash. [PDF]

Micromachines (Basel), 2023
Jia J, Jin L, You K, Zhu A.
europepmc   +1 more source

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory. [PDF]

Micromachines (Basel), 2023
You K, Jin L, Jia J, Huo Z.
europepmc   +1 more source

Optimizing Cell Structure to Improve Cell Characteristics in IGZO Channel-Based 3D NAND Flash With p-Type Gate

IEEE Access
For the first time, a novel IGZO channel-based 3D NAND Flash structure with an embedded p-type poly-Si injection layer is proposed, using integrated structural, material, and operational modifications to address the limitations of the conventional IGZO ...
Sungho Park, Youngho Jung, Daewoong Kang
doaj   +1 more source

Modeling methodology for thermo-structural analysis of V-NAND flash memory structure

Scientific Reports
This study proposes modeling methodology based on a continuous model for conducting thermo-electric-structural analyses of V-NAND flash memory structure under the Joule heating effect.
Yongha Kim, Seungjun Ryu, Sungryung Lee
doaj   +1 more source

Impact of Program–Erase Operation Intervals at Different Temperatures on 3D Charge-Trapping Triple-Level-Cell NAND Flash Memory Reliability

Micromachines
Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost.
Xuesong Zheng, Yifan Wu, Haitao Dong, Yizhi Liu, Pengpeng Sang, Liyi Xiao, Xuepeng Zhan   +6 more
doaj   +1 more source

A physics-guided surrogate modeling framework for RDF-dominated variability and bit-error rate analysis of 3D NAND flash memory

Discover Applied Sciences
Three-dimensional (3D) NAND flash memory has become the dominant non-volatile storage technology due to its high density and scalability. However, aggressive vertical stacking introduces significant threshold-voltage (VT) variability that affects device ...
Dikendra Kumar Verma, Anurag Vidyarthi, Upendra Mohan Bhatt   +2 more
doaj   +1 more source

Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory

IEEE Journal of the Electron Devices Society
In this paper, we propose a low-power stack-level programming scheme for ultrahigh stack 3D NAND flash memory. As the number of word lines (WLs) increases beyond 300 layers, the increased pass voltage leads to excessive power consumption and reliability ...
Kyungmin Lee, Gunwook Yoon, Seung Jae Baik, Myounggon Kang   +3 more
doaj   +1 more source

Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider V_th Window in 3D NAND Flash Using a Machine-Learning Method. [PDF]

Nanomaterials (Basel), 2022
Nam K, Park C, Yoon JS, Yun H, Jang H, Cho K, Kang HJ, Park MS, Sim J, Choi HC, Baek RH.   +10 more
europepmc   +1 more source

Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories. [PDF]

Micromachines (Basel), 2021
Ramesh S, Ajaykumar A, Ragnarsson LÅ, Breuil L, El Hajjam GK, Kaczer B, Belmonte A, Nyns L, Soulié JP, Van den Bosch G, Rosmeulen M.   +10 more
europepmc   +1 more source