Nanoplate FET와 3D NAND Flash Memory에서 Self Heating Effect 분석 [PDF]
, 2020 학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 신형철.In this thesis, self-heating effects (SHEs) in three-stacked nanoplate FETs were investigated majorly through the TCAD simulation over various logic device nodes.
김현석
core
MicromachinesThe program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction
Kaikai You +3 more
doaj +1 more source
Analysis of Electrostatic Crosstalk in 3D Vertical NAND Charge Trapping Memory with Junction less GAA Nanowire FET [PDF]
, 2012 The electrostatic crosstalk in the 3D vertical CTM (Charge Trapping Memory) NAND NVM is investigated with various typical operation conditions. The junctionless FET of GAA (Gate-All-Around) nanowire with O/N/O (Oxide/Nitride/Oxide) dielectrics is ...
Kang, Jinfeng +11 more
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White Light Interference Solution for Novel 3D NAND VIA Dishing Metrology
Journal of Microelectronic Manufacturing, 2019 In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher, peripheral circuits may account for more than 50% of ...
Xiaoye Ding +5 more
doaj +1 more source
layer granularity refresh for improving performance and lifetime of 3D NAND flash memory [PDF]
, 2023 학위논문(석사) - 한국과학기술원 : 전산학부, 2023.2,[iv, 33 p. :]NAND flash refresh schemes have been proposed to mitigate retention errors by remapping pages before excessive errors occur in them.
Kim, Hyungsoon
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Investigation of the Connection Schemes between Decks in 3D NAND Flash. [PDF]
Micromachines (Basel), 2023 Jia J, Jin L, You K, Zhu A.
europepmc +1 more source
HAIPO: Hybrid AI Algorithm-Based Post-Fabrication Optimization for Modern 3D NAND Flash Memory [PDF]
To successfully meet the various requirements of modern storage systems, NAND flash memory should be highly optimized by precisely tuning a huge number of internal operating parameters. Although 3D NAND flash memory succeeds in increasing the capacity of
Myungsuk Kim
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Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory. [PDF]
Micromachines (Basel), 2023 You K, Jin L, Jia J, Huo Z.
europepmc +1 more source
COTS 3D NAND Flash: SEE Test Results and Challenges [PDF]
, 2018 Heavy-ion test data for 3D NAND flash memories is presented, along with a discussion of modern testing challenges and near-term plans for a broad survey of currently-available product ...
Campola, Michael +2 more
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An Erase Efficiency Boosting Strategy for 3D Charge Trap NAND Flash [PDF]
, 2018 Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory.
Yu-Pei Liang +5 more
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