Results 51 to 60 of about 26,595 (187)
Universal Three Dimensional Optical Logic
Modern integrated circuits are essentially two-dimensional (2D). Partial three-dimensional (3D) integration and 3D-transistor-level integrated circuits have long been anticipated as routes to improve the performance, cost and size of electronic computing
Ensley, Mcleod, Miller, Minardi, Solli
core +1 more source
Two-dimensional DCT/IDCT architecture [PDF]
A fully parallel architecture for the computation of a two-dimensional (2-D) discrete cosine transform (DCT), based on row-column decomposition is presented.
Aggoun, A, Jollah, I
core +1 more source
Antisite Domains in Double Perovskite Ferromagnets: Impact on Magnetotransport and Half-metallicity
Several double perovskite materials of the form A_2BB'O_6 exhibit high ferromagnetic T_c, and significant low field magnetoresistance. They are also a candidate source of spin polarized electrons.
Aguilar B. +5 more
core +1 more source
Framework to Enhance Teaching and Learning in System Analysis and Unified Modelling Language [PDF]
Cowling, MA ORCiD: 0000-0003-1444-1563; Munoz Carpio, JC ORCiD: 0000-0003-0251-5510Systems Analysis modelling is considered foundational for Information and Communication Technology (ICT) students, with introductory and advanced units included in nearly ...
Birt, James R. +2 more
core +2 more sources
Atomic Layer Deposition in Transistors and Monolithic 3D Integration
Transistors are fundamental building blocks of modern electronics. This review summarizes recent progress in atomic layer deposition (ALD) for the synthesis of two‐dimensional (2D) metal oxides and transition‐metal dichalcogenides (TMDCs), with particular emphasis on their enabling role in monolithic three‐dimensional (M3D) integration for next ...
Yue Liu +5 more
wiley +1 more source
An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND
3D NAND is a great architectural innovation in the field of flash memory. The staircase for control gate is a unique and important process in the manufacturing of 3D NAND.
Peizhen Hong +7 more
doaj +1 more source
Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory
In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss.
Fei Wang +3 more
doaj +1 more source
Evolution of Materials and Device Stacks for HfO2‐Based Ferroelectric Memories
This review summarizes engineering strategies for HfO2 based ferroelectric memories with focus on FeCAP and FeFET structures. It describes how dopant design, stress effects, and interface engineering improve the bulk ferroelectric response. It further discusses how channel engineering supports reliable memory characteristics and scalable integration ...
Eunjin Kim, Jiyong Woo
wiley +1 more source
Embodied Carbon Footprint of 3D NAND Memories
This study presents a novel model for estimating the embodied carbon footprint of Solid-State Drives (SSDs), focusing on the relationship between manufacturing complexity and environmental impact. By analyzing the number of process steps required to fabricate SSDs, particularly those using 3D NAND technology, the model predicts carbon emissions without
Olivier Weppe +6 more
openaire +2 more sources
Transducers convert physical signals into electrical and optical representations, yet each mechanism is bounded by intrinsic trade‐offs across bandwidth, sensitivity, speed, and energy. This review maps transduction mechanisms across physical scale and frequency, showing how heterogeneous integration and multiphysics co‐design transform isolated ...
Aolei Xu +8 more
wiley +1 more source

