Recently, a new structure called PUC has been introduced, in which the periphery is located below the NAND cell to reduce chip area. However, as the SiN-based cell alloy process progresses during the NAND manufacturing process, there is a problem in that
Eunyoung Park, Hyun-Yong Yu
doaj +1 more source
Enhanced programming efficiency in vertical NAND flash using self-boosting hot carrier injection. [PDF]
Kim M +6 more
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Enabling scalable ferroelectric-based future generation vertical NAND flash with bonding-friendly architecture: strategies for erase and disturb optimization. [PDF]
Song I, Kim J, Lee S, Myeong I.
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Spatially programmable origami networks enable high-density mechanical computing for autonomous robotics. [PDF]
Hu X, Tan T, Chen Y, Yan Z.
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A functionally complete logic gate in a soft photoresponsive hydrogel. [PDF]
Mahmood F +3 more
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MoS<sub>2</sub> Channel-Enhanced High-Density Charge Trap Flash Memory and Machine Learning-Assisted Sensing Methodologies for Memory-Centric Computing Systems. [PDF]
Kim KH +7 more
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Hafnium-Based Ferroelectric Diodes for Logic-in-Memory Application. [PDF]
Han S +10 more
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Advancing the Frontiers of HfO<sub>2</sub>-Based Ferroelectric Memories: Innovative Concepts from Materials to Applications. [PDF]
Zhou Z +9 more
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Universal Logic-in-Memory Gates Using Reconfigurable Silicon Transistors. [PDF]
Kim S, Kim N, Ko Y, Lim D.
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