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Issues and Key Technologies for Next Generation 3D NAND
2021 International Conference on Electronics, Information, and Communication (ICEIC), 2021In this paper, design challenges and key technologies to overcome the hurdles for the future 3D NAND are introduced. More specifically, state-of-the-art solutions for higher density, lower cost and higher bandwidth NAND is covered in detail.
Chi-Weon Yoon +4 more
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3D Stacked NAND Flash Memories
2016Market request for bigger and cheaper NAND Flash memories triggers continuous research activity for cell size shrinkage. For many years, workarounds for all the scalability issues of planar Flash memories have been found. Some examples are the improved programming algorithms for controlling electrostatic interference between adjacent cells [6], and the
Rino Micheloni, Luca Crippa
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Overview of 3D NAND Flash and progress of split-page 3D vertical gate (3DVG) NAND architecture
2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014This paper provides an overview of various 3D NAND Flash memory devices and a comprehensive understanding of 3DVG architectures. Compared with conventional floating gate Flash memory devices, charge-trapping (CT) devices provide much simpler 3D process integration with smaller footprint thus are naturally suitable for 3D NAND.
Pei-Ying Du +4 more
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2015
Because NAND Flash possesses several advantages such as very high density, low cost, low power consumption, high programming and reading throughput, and compact form factor, it has been widely adopted as a necessary key component of most modern consumer electronics.
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Because NAND Flash possesses several advantages such as very high density, low cost, low power consumption, high programming and reading throughput, and compact form factor, it has been widely adopted as a necessary key component of most modern consumer electronics.
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3D NAND Flash Status and Trends
2022 IEEE International Memory Workshop (IMW), 2022Lars Heineck, Jin Liu
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3D analysis of high-aspect ratio features in 3D-NAND
Metrology, Inspection, and Process Control for Microlithography XXXIV, 2020We demonstrate the application of 3D tomography by FIB-SEM to analyze channel holes in 3D-NAND. We automatically analyze the 3D channel profiles for size, shape, and placement from the reconstructed full 3D volume. As the data contains thousands of holes, and each hole is sampled with a resolution of a few nanometer in 3D, this method provides a vast ...
Jens-Timo Neumann +8 more
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Impact of Mechanical Stress on the Electrical Performance of 3D NAND
2019 IEEE International Reliability Physics Symposium (IRPS), 2019We have developed a methodology for analyzing the impact of mechanical stress on the electrical performance of 3D NAND devices. The methodology relies on in-situ electrical characterization of 3D NAND flash memory under application of an external load with a nanoindenter. The forces applied in the experiment are converted to stress using finite element
Anastasiia Kruv +6 more
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Overview of 3D NAND Technologies and Outlook Invited Paper
2018 Non-Volatile Memory Technology Symposium (NVMTS), 2018In this paper, 3D NAND floating gate (FG) and charge trap (CT) cell fundamentals, advantages and challenges are discussed. Future scaling options and associated challenges from fabrication process integration, equipment engineering is briefly presented.
Srinath Venkatesan, Marc Aoulaiche
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Reliability of 3D NAND Flash Memories
2016In this chapter the main reliability mechanisms affecting 3D NAND memories will be addressed, providing a comparison between 3D FG and 3D CT devices in terms of reliability and expected performances. Starting from an analysis of basic reliability issues related to both physical and architectural aspects affecting NAND memories, the specific physical ...
GROSSI, Alessandro +2 more
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Opportunities and challenges of 3D NAND scaling
2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 20133D NAND is attracting increasing attention as a NAND scaling solution. In 3D NAND, the physical cell size is decoupled from the effective cell size by stacking multiple tiers. This enables effective NAND cell size scaling without degrading cell performance and reliability. However, 3D process integration could introduce new sources of cell degradation.
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