Results 131 to 140 of about 26,595 (187)

Characterizing 3D Floating Gate NAND Flash

ACM Transactions on Storage, 2018
As both NAND flash memory manufacturers and users are turning their attentions from planar architecture towards three-dimensional (3D) architecture, it becomes critical and urgent to understand the characteristics of 3D NAND flash memory. These characteristics, especially those different from planar NAND flash, can significantly affect design choices ...
Qin Xiong, Fei Wu, Zhonghai Lu
exaly   +2 more sources

Modeling and Optimization of Advanced 3D NAND Memory

2020 Device Research Conference (DRC), 2020
Development of a new complex technology such as 3D NAND requires significant efforts in terms of materials screening, process tuning, and device design leading to fabrication and characterization of many test wafers with significant time-to-market cost. In this context, modeling can help accelerate 3D NAND technology development.
Mehdi Saremi, Ashish Pal, Liu Jiang, El Mehdi Bazizi, Helen Lee, Xi-Wei Lin, Blessy Alexander, Buvna Ayyagari-Sangamalli   +7 more
openaire   +1 more source

Reliability of Mo as Word Line Metal in 3D NAND

2021 IEEE International Reliability Physics Symposium (IRPS), 2021
We evaluate the reliability of Mo as word line metal for 3-D NAND Flash devices, by mimicking the stacked architecture using planar capacitors with SiO 2 /Al 2 O 3 and SiO 2 /HfO 2 dielectric stacks. By combining TDDB and TVS measurements with simulations, we show that Mo does not drift in the two examined stacks.
Davide Tierno, Kristof Croes, Arjun Ajaykumar, Siva Ramesh, Geert Van den Bosch, Maarten Rosmeulen   +5 more
openaire   +1 more source

An alternative to Tungsten in 3D-NAND technology

2021 IEEE International Interconnect Technology Conference (IITC), 2021
As the number of wordlines has reached 128 layers in the realm of 3D-NAND, several challenges have emerged to produce these structures. Among these is metallization of the connection made with Tungsten. This paper explores Nickel alloys as an alternative metal. Several key data are presented to validate this new concept.
Suhr Dominique, Mevellec Vincent, Thiam Mikailou, Idier Jonathan, Raynal Frederic, Berthon Hermine, Perrault Elisa, Hann Nicolas, Doussot Celine, Kim Yeeseul, Baus Mathilde, Lakhdari Amine, Guittet Gaelle, Caillard Louis   +13 more
openaire   +1 more source

3D RRAM design and benchmark with 3d NAND FLASH

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
The monolithic 3D integration of resistive switching random access memory (RRAM) is one attractive approach to build high-density non-volatile memory. In this paper, the design considerations of 3D vertical RRAM architecture are presented from the device, circuit to system level. Due to the voltage drop and sneak path problem, the sub-array size of the
Pai-Yu Chen, Cong Xu, Yuan Xie, Shimeng Yu   +3 more
openaire   +1 more source

Issues and Key Technologies for Next Generation 3D NAND

2021 International Conference on Electronics, Information, and Communication (ICEIC), 2021
In this paper, design challenges and key technologies to overcome the hurdles for the future 3D NAND are introduced. More specifically, state-of-the-art solutions for higher density, lower cost and higher bandwidth NAND is covered in detail.
Chiweon Yoon, Hyunggon Kim, Seon-Kyoo Lee, Jinyub Lee, Jai Hyuk Song   +4 more
openaire   +1 more source

3D NAND Flash Memories

2018
Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.
Rino Micheloni, Seiichi Aritome, Luca Crippa   +2 more
openaire   +1 more source

3D analysis of high-aspect ratio features in 3D-NAND

Metrology, Inspection, and Process Control for Microlithography XXXIV, 2020
We demonstrate the application of 3D tomography by FIB-SEM to analyze channel holes in 3D-NAND. We automatically analyze the 3D channel profiles for size, shape, and placement from the reconstructed full 3D volume. As the data contains thousands of holes, and each hole is sampled with a resolution of a few nanometer in 3D, this method provides a vast ...
Jens-Timo Neumann, Dmitry Klochkov, Thomas Korb, Sheetal B. Gupta, Amir Avishai, Ramani Pichumani, Keum Sil Lee, Alex Buxbaum, Eugen Foca   +8 more
openaire   +1 more source

Overview of 3D NAND Flash and progress of split-page 3D vertical gate (3DVG) NAND architecture

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
This paper provides an overview of various 3D NAND Flash memory devices and a comprehensive understanding of 3DVG architectures. Compared with conventional floating gate Flash memory devices, charge-trapping (CT) devices provide much simpler 3D process integration with smaller footprint thus are naturally suitable for 3D NAND.
Pei-Ying Du, Hang-Ting Lue, Yen-Hao Shih, Kuang-Yeu Hsieh, Chih-Yuan Lu   +4 more
openaire   +1 more source

3D Stacked NAND Flash Memories

2016
Market request for bigger and cheaper NAND Flash memories triggers continuous research activity for cell size shrinkage. For many years, workarounds for all the scalability issues of planar Flash memories have been found. Some examples are the improved programming algorithms for controlling electrostatic interference between adjacent cells [6], and the
Rino Micheloni, Luca Crippa
openaire   +1 more source