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Band and Field Coengineered Charge Trap Memristor via Au Nanoparticle Layer for Programming Speed Enhancement. [PDF]

Small Sci
Kim G, Park J, Park W, Ko M, Lee MG, Cho H, Kim KM.   +6 more
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Ferroelectric 3D NAND Storage (Invited)

2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
In this work, we report a multi-pronged optimization of band engineered ferroelectric field effect transistors with dielectric inserts for NAND solutions for in-storage compute applications: (1) design space exploration for optimizing memory window (MW ...
Prasanna Venkatesan, Asif Khan
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3D Charge Trap NAND Flash Memories

ECS Transactions, 2016
This chapter starts off with 2 vertical channel architectures named BiCS (Bit Cost Scalable) and P-BiCS (Pipe-Shaped BiCS), respectively. BiCS was proposed for the first time by Toshiba in 2007, and another version called P-BiCS was presented in 2009 to improve retention, source selector performances and source line resistance.
Luca Crippa, Rino Micheloni
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Characterizing 3D Floating Gate NAND Flash

Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2017
In this paper, we characterize a state-of-the-art 3D floating gate NAND flash memory through comprehensive experiments on an FPGA platform. Then, we present distinct observations on performance and reliability, such as operation latencies and various error patterns. We believe that through our work, novel 3D NAND flash-oriented designs can be developed
Qin Xiong, Fei Wu, Zhonghai Lu, Yue Zhu, You Zhou, Yibing Chu, Changsheng Xie, Ping Huang   +7 more
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Characterizing 3D Floating Gate NAND Flash

ACM Transactions on Storage, 2018
As both NAND flash memory manufacturers and users are turning their attentions from planar architecture towards three-dimensional (3D) architecture, it becomes critical and urgent to understand the characteristics of 3D NAND flash memory. These characteristics, especially those different from planar NAND flash, can significantly affect design choices ...
Qin Xiong, Fei Wu, Zhonghai Lu, Yue Zhu, You Zhou, Yibing Chu, Changsheng Xie, Ping Huang   +7 more
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TCAD Based Study of String Current Variability in 3D NAND Flash Memory

International Conference on VLSI Design
3D NAND memory has become indispensable for high-density data storage, offering superior scalability and cost-efficiency. However, with shrinking memory cell sizes and increasing cell densities, precise control over fabrication parameters is crucial for ...
Mrinmoy Mahapatra, Prathamesh Kekarjawlekar, A. K.   +2 more
semanticscholar   +1 more source

3D NAND Flash Memories

2018
Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.
Rino Micheloni, Seiichi Aritome, Luca Crippa   +2 more
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3D reconstruction of 3D NAND memory etch profiles using FIB-SEM: identifying variances in etched hole patterns

Advanced Lithography
The semiconductor industry plays a pivotal role in advancing various global technology sectors, such as data processing and artificial intelligence, which drive the need for ongoing innovation.
Jin Zhang, Keumsil Lee, D. Klochkov, Thomas Korb, Osman Sorkhabi, Tian Lan, Ramani Pichumani, Kina Tekleyohannes, Junyu Wang, Shawn Sallis, Sean Ningen, HyunHwa Kim, Tiffany Teoh, Yevgen Polubotko, David Pirkle, Eugen Foca   +15 more
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3D Stacked NAND Flash Memories

2016
Market request for bigger and cheaper NAND Flash memories triggers continuous research activity for cell size shrinkage. For many years, workarounds for all the scalability issues of planar Flash memories have been found. Some examples are the improved programming algorithms for controlling electrostatic interference between adjacent cells [6], and the
Rino Micheloni, Luca Crippa
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Overview of 3D NAND Flash and progress of split-page 3D vertical gate (3DVG) NAND architecture

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
This paper provides an overview of various 3D NAND Flash memory devices and a comprehensive understanding of 3DVG architectures. Compared with conventional floating gate Flash memory devices, charge-trapping (CT) devices provide much simpler 3D process integration with smaller footprint thus are naturally suitable for 3D NAND.
Pei-Ying Du, Hang-Ting Lue, Yen-Hao Shih, Kuang-Yeu Hsieh, Chih-Yuan Lu   +4 more
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