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Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory

IEEE Journal of the Electron Devices Society
In this paper, we propose a low-power stack-level programming scheme for ultrahigh stack 3D NAND flash memory. As the number of word lines (WLs) increases beyond 300 layers, the increased pass voltage leads to excessive power consumption and reliability ...
Kyungmin Lee, Gunwook Yoon, Seung Jae Baik, Myounggon Kang   +3 more
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Overview of emerging nonvolatile memory technologies [PDF]

, 2014

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Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next‐Generation High‐Density Storage Systems

Advanced Science
Multilevel storage and low‐voltage operation position ferroelectric transistors as promising candidates for next‐generation nonvolatile memory. Among them, gate‐injection‐type ferroelectric transistors offer improved vertical scalability and power ...
Giuk Kim, Sangho Lee, Hyojun Choi, Yangjin Jung, Woongjin Kim, Sanghyun Park, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Mincheol Shin, Jinho Ahn, Sanghun Jeon   +12 more
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3D Charge Trap NAND Flash Memories

ECS Transactions, 2016
This chapter starts off with 2 vertical channel architectures named BiCS (Bit Cost Scalable) and P-BiCS (Pipe-Shaped BiCS), respectively. BiCS was proposed for the first time by Toshiba in 2007, and another version called P-BiCS was presented in 2009 to improve retention, source selector performances and source line resistance.
Luca Crippa, Rino Micheloni
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Characterizing 3D Floating Gate NAND Flash

Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2017
In this paper, we characterize a state-of-the-art 3D floating gate NAND flash memory through comprehensive experiments on an FPGA platform. Then, we present distinct observations on performance and reliability, such as operation latencies and various error patterns. We believe that through our work, novel 3D NAND flash-oriented designs can be developed
Qin Xiong, Fei Wu, Zhonghai Lu, Yue Zhu, You Zhou, Yibing Chu, Changsheng Xie, Ping Huang   +7 more
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Characterizing 3D Floating Gate NAND Flash

ACM Transactions on Storage, 2018
As both NAND flash memory manufacturers and users are turning their attentions from planar architecture towards three-dimensional (3D) architecture, it becomes critical and urgent to understand the characteristics of 3D NAND flash memory. These characteristics, especially those different from planar NAND flash, can significantly affect design choices ...
Qin Xiong, Fei Wu, Zhonghai Lu, Yue Zhu, You Zhou, Yibing Chu, Changsheng Xie, Ping Huang   +7 more
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3D NAND Flash Memories

2018
Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.
Rino Micheloni, Seiichi Aritome, Luca Crippa   +2 more
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3D Stacked NAND Flash Memories

2016
Market request for bigger and cheaper NAND Flash memories triggers continuous research activity for cell size shrinkage. For many years, workarounds for all the scalability issues of planar Flash memories have been found. Some examples are the improved programming algorithms for controlling electrostatic interference between adjacent cells [6], and the
Rino Micheloni, Luca Crippa
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Reliability challenges in 3D NAND Flash memories

2019 IEEE 11th International Memory Workshop (IMW), 2019
The reliability of 3D NAND Flash memory technology is depending on many factors. Most of them are related to the process-induced variability of the layers. Endurance, data retention capabilities, and cross-temperature immunity are the metrics that become affected by this, turning in peculiar reliability challenges that are difficult to be tackled ...
Zambelli C., Micheloni R., Olivo P.
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3D RRAM design and benchmark with 3d NAND FLASH

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
The monolithic 3D integration of resistive switching random access memory (RRAM) is one attractive approach to build high-density non-volatile memory. In this paper, the design considerations of 3D vertical RRAM architecture are presented from the device, circuit to system level. Due to the voltage drop and sneak path problem, the sub-array size of the
Pai-Yu Chen, Cong Xu, Yuan Xie, Shimeng Yu   +3 more
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