Results 81 to 90 of about 5,102 (147)
Modeling methodology for thermo-structural analysis of V-NAND flash memory structure
This study proposes modeling methodology based on a continuous model for conducting thermo-electric-structural analyses of V-NAND flash memory structure under the Joule heating effect.
Yongha Kim, Seungjun Ryu, Sungryung Lee
doaj +1 more source
Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic [PDF]
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Chen, Shuo Han
core
Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost.
Xuesong Zheng +6 more
doaj +1 more source
A Behavioral Compact Model of 3D NAND Flash Memory
We present a behavioral compact model of 3D NAND flash memory for integrated circuits and system-level applications. This model is easy to implement, computationally efficient, fast, accurate and effectively accounts for the different parasitic capacitance coupling effects applicable to the 3D geometry of the vertical channel Macaroni body charge-trap ...
Sahay, Shubham, Strukov, Dmitri
openaire +2 more sources
For the first time, a novel IGZO channel-based 3D NAND Flash structure with an embedded p-type poly-Si injection layer is proposed, using integrated structural, material, and operational modifications to address the limitations of the conventional IGZO ...
Sungho Park, Youngho Jung, Daewoong Kang
doaj +1 more source
Wordline Input Bias Scheme for Neural Network Implementation in 3D-NAND Flash
In this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs).
Hwiho Hwang +3 more
doaj +1 more source
A TID and SEE Characterization of Multi-Terabit COTS 3D NAND Flash [PDF]
Single-event effects and total ionizing dose testing is described for a 32-layer NAND flash memory, in both SLC and MLC configurations, with special considerations for unique three-dimensional test ...
Campola, Michael J., Wilcox, Edward P.
core +1 more source
In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj +1 more source
The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction
Kaikai You +3 more
doaj +1 more source
Oxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field‐effect mobility and superior large‐area uniformity but suffering from low thermal stability, trade‐off between mobility and stability, and the
Su‐Hwan Choi +15 more
doaj +1 more source

