Results 91 to 100 of about 4,160 (185)

A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory With Separated Source-Line

IEEE Access
In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj   +1 more source

Dependability Assessment of NAND Flash-memory for Mission-critical Applications [PDF]

It is a matter of fact that NAND flash memory devices are well established in consumer market. However, it is not true that the same architectures adopted in the consumer market are suitable for mission critical applications like space.
Fabiano, Michele
core  

Unveiling the Hybrid‐Channel (poly‐Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL‐Assisted Erase Operation

Small Structures
Oxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field‐effect mobility and superior large‐area uniformity but suffering from low thermal stability, trade‐off between mobility and stability, and the
Su‐Hwan Choi, Jae‐Min Sim, Jeongmin Shin, Seong‐Hwan Ryu, Taewon Hwang, So Young Lim, Hye‐Jin Oh, Jae‐Hyeok Kwag, Jun‐Yeoub Lee, Ki‐Cheol Song, Yeonhee Lee, Minju Song, Junghwan Kim, Chang‐Kyun Park, Yun‐Heub Song, Jin‐Seong Park   +15 more
doaj   +1 more source

Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory

IEEE Journal of the Electron Devices Society
In this paper, we propose a low-power stack-level programming scheme for ultrahigh stack 3D NAND flash memory. As the number of word lines (WLs) increases beyond 300 layers, the increased pass voltage leads to excessive power consumption and reliability ...
Kyungmin Lee, Gunwook Yoon, Seung Jae Baik, Myounggon Kang   +3 more
doaj   +1 more source

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories

ACM Transactions on Architecture and Code Optimization
With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory.
Qiao Li, Yu Chen, Guanyu Wu, Yajuan Du, Min Ye, Xinbiao Gan, Jie Zhang, Zhirong Shen, Jiwu Shu, Chun Xue   +9 more
openaire   +1 more source

Overview of emerging nonvolatile memory technologies [PDF]

, 2014

core   +1 more source

Investigation of the Connection Schemes between Decks in 3D NAND Flash. [PDF]

Micromachines (Basel), 2023
Jia J, Jin L, You K, Zhu A.
europepmc   +1 more source

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash. [PDF]

Micromachines (Basel), 2023
Yang T, Zhang B, Wang Q, Jin L, Xia Z.
europepmc   +1 more source

Enhanced programming efficiency in vertical NAND flash using self-boosting hot carrier injection. [PDF]

Sci Rep
Kim M, Hong J, Kim C, Kim SJ, Hwang S, Baik SJ, Jeon J.   +6 more
europepmc   +1 more source

Enabling scalable ferroelectric-based future generation vertical NAND flash with bonding-friendly architecture: strategies for erase and disturb optimization. [PDF]

Nanoscale Adv
Song I, Kim J, Lee S, Myeong I.
europepmc   +1 more source