Results 91 to 100 of about 4,190 (193)

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

IEEE Access, 2019
NAND flash memory is widely used in various computing systems. However, flash blocks can sustain only a limited number of program/erase (P/E) cycles, which are referred to as the endurance.
Ruixiang Ma, Fei Wu, Meng Zhang, Zhonghai Lu, Jiguang Wan, Changsheng Xie   +5 more
doaj   +1 more source

Probing defects in 3D NAND flash memory with temperature-dependent leakage current [PDF]

AIP Advances
This study investigated the defect profiles of highly stacked 3D NAND flash memory using trap-assisted leakage current analysis. By extracting the activation energy (Ea), we examined leakage mechanisms under hydrogen (H) and fluorine (F) gas annealing ...
Donghyun Kim, Sae-In Bang, Ki Seok Heo, Seoyeon Choi, Jungchun Kim, Seunghee Jin, Minjung Kim, Eunmee Kwon, Jae Woo Lee   +8 more
doaj   +1 more source

A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory With Separated Source-Line

IEEE Access
In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj   +1 more source

Unveiling the Hybrid‐Channel (poly‐Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL‐Assisted Erase Operation

Small Structures
Oxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field‐effect mobility and superior large‐area uniformity but suffering from low thermal stability, trade‐off between mobility and stability, and the
Su‐Hwan Choi, Jae‐Min Sim, Jeongmin Shin, Seong‐Hwan Ryu, Taewon Hwang, So Young Lim, Hye‐Jin Oh, Jae‐Hyeok Kwag, Jun‐Yeoub Lee, Ki‐Cheol Song, Yeonhee Lee, Minju Song, Junghwan Kim, Chang‐Kyun Park, Yun‐Heub Song, Jin‐Seong Park   +15 more
doaj   +1 more source

NASA Electronic Parts and Packaging (NEPP) Program Plans [PDF]

This presentation provides an overview of the NEPP ...
Label, Kenneth A., Sampson, Michael J.
core   +1 more source

Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory

IEEE Journal of the Electron Devices Society
In this paper, we propose a low-power stack-level programming scheme for ultrahigh stack 3D NAND flash memory. As the number of word lines (WLs) increases beyond 300 layers, the increased pass voltage leads to excessive power consumption and reliability ...
Kyungmin Lee, Gunwook Yoon, Seung Jae Baik, Myounggon Kang   +3 more
doaj   +1 more source

Overview of emerging nonvolatile memory technologies [PDF]

, 2014

core   +1 more source

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories

ACM Transactions on Architecture and Code Optimization
With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory.
Qiao Li, Yu Chen, Guanyu Wu, Yajuan Du, Min Ye, Xinbiao Gan, Jie Zhang, Zhirong Shen, Jiwu Shu, Chun Xue   +9 more
openaire   +1 more source

Investigation of the Connection Schemes between Decks in 3D NAND Flash. [PDF]

Micromachines (Basel), 2023
Jia J, Jin L, You K, Zhu A.
europepmc   +1 more source

Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack. [PDF]

Nano Lett
Fernandes L, Wodzro S, Venkatesan P, Ravikumar P, Lee MY, Shon M, Chakraborty D, Song T, Kang S, Soliman S, Tian M, Yeager J, Adler J, Chen J, Wang Z, Wolfe D, Yu S, Padovani A, Datta S, Ray B, Khan A.   +20 more
europepmc   +1 more source