Results 121 to 130 of about 485 (168)

Optimization of Performance and Reliability in 3D NAND Flash Memory

IEEE Electron Device Letters, 2020
3D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO2 (O1) layer thickness near poly Si channel in the tunnel layer based on SiO2/SiOxNy/SiO2 structure.
Yingjie Ouyang, Zhiliang Xia, Tao Yang, Dandan Shi, Wenxi Zhou, Zongliang Huo   +5 more
openaire   +1 more source

A cell current compensation scheme for 3D NAND FLASH memory

2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015
The 3D NAND, so-called vertical NAND has cell Vt degradation especially in low temperature, and it affects cell Vt distribution and shift when NAND operates. To solve this problem, the temperature compensation scheme by ATS(Analog Temp Sensor) using CTAT circuit has proposed.
Sungwook Choi, KyuTae Park, Marco Passerini, HeeJoung Park, DoYoung Kim, ChiHyun Kim, Kunwoo Park, Jinwoong Kim   +7 more
openaire   +2 more sources

Microscopic Physical Origin of Charge Traps in 3D NAND Flash Memories

Extended Abstracts of the 2022 International Conference on Solid State Devices and Materials, 2022
Abstract We performed the first-principles calculations for a nitrogen vacancy (V N) and hydrogen(H) atom in β-Si3N4 to clarify the atomistic origin of charge traps in silicon nitride (SiN) layers and charge-trapping mechanism used for 3D NAND flash memories.
Fugo Nanataki, Jun-Ichi Iwata, Kenta Chokawa, Masaaki Araidai, Atsushi Oshiyama, Kenji Shiraishi   +5 more
openaire   +1 more source

3D Floating Gate NAND Flash Memories

2016
Planar NAND Flash memories (commercially available) are based on Floating Gate, which has been developed and engineered for many decades. Therefore, there have been many attempts to develop 3D Floating Gate cells in order to re-use all the know-how cumulated over time.
Rino Micheloni, Luca Crippa
openaire   +1 more source

Characteristics of Junctionless Charge Trap Flash Memory for 3D Stacked NAND Flash

Journal of Nanoscience and Nanotechnology, 2013
The electrical characteristics of tunnel barrier engineered-charge trap flash (TBE-CTF) memory devices with junctionless (JL) source and drain (S/D) were investigated. The JL structure is composed of an n(+)-poly-Si based ultra-thin channel and S/D with identical doping concentrations.
Jinho, Oh, Heedo, Na, Sunghoon, Park, Hyunchul, Sohn   +3 more
openaire   +2 more sources

Error Generation for 3D NAND Flash Memory

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022
Weihua Liu, Fei Wu 0005, Songmiao Meng, Xiang Chen 0028, Changsheng Xie 0001   +4 more
openaire   +1 more source

3D VG-Type NAND Flash Memories

2016
The common feature among the different 3D NAND solutions is constituted by very deep vertical (z direction) etching steps that define the Flash cells geometries simultaneously. Transistor geometries are formed by the deep trench through a multiple polysilicon/oxide stack.
openaire   +1 more source

Study on cell shape in 3D NAND flash memory

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2015
All kinds of cell structures are appeared in 3D NAND flash technologies and all seem to be promising. In this paper, detail comparisons among the cell structures of them are presented. The theoretical derivation and simulation results both support that the cylindrical cell structure has better program/erase speed and memory window.
Wei Feng, Nine Deng
openaire   +1 more source

Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory

2019 IEEE International Reliability Physics Symposium (IRPS), 2019
3D NAND flash memory has entered dynamically into the space of enterprise server and storage systems, offering significantly higher capacity and better endurance than the latest 2D technology node. Moreover, the advancements in vertical stacking, cell design and program/read algorithms, have also enabled TLC 3D NAND flash with enterprise-level ...
Nikolaos Papandreou, Haralampos Pozidis, Thomas P. Parnell, Nikolas Ioannou, Roman A. Pletka, Sasa Tomic, Patrick Breen, Gary A. Tressler, Aaron Fry, Timothy Fisher   +9 more
openaire   +2 more sources

Vertical-channel stacked array (VCSTAR) for 3D NAND flash memory

2011 International Semiconductor Device Research Symposium (ISDRS), 2011
Abstract A novel three-dimensional (3D) NAND flash memory, VCSTAR (Vertical-Channel STacked ARray), is investigated. The proposed device is a vertical channel structure having stacked word-lines to achieve high memory density without shrinking cell channel length.
Se Hwan Park, Yoon Kim, Wandong Kim, Joo Yun Seo, Byung-Gook Park   +4 more
openaire   +1 more source