Results 31 to 40 of about 3,421,577 (197)

Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next‐Generation High‐Density Storage Systems [PDF]

Advanced Science
Multilevel storage and low‐voltage operation position ferroelectric transistors as promising candidates for next‐generation nonvolatile memory. Among them, gate‐injection‐type ferroelectric transistors offer improved vertical scalability and power ...
Giuk Kim, Sangho Lee, Hyojun Choi, Yangjin Jung, Woongjin Kim, Sanghyun Park, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Mincheol Shin, Jinho Ahn, Sanghun Jeon   +12 more
doaj   +2 more sources

Nitrogen‐Doped GeTeS Ovonic Threshold Switching Selector With Optimized Performance Trade‐Off for 1S–1R Phase‐Change Memory [PDF]

Small, Volume 22, Issue 53, 21 September 2026.
This study introduced a Ge‐Te‐S co‐sputtering process to resolve the performance trade‐off between GeTe and GeS in OTS selector devices, and improved device durability through nitrogen doping. Furthermore, in a 1S‐1R structure incorporating phase‐change memory devices, it simultaneously achieved excellent thermal stability, durability, high‐speed ...
Min Su Kang, Jong Min Joo, Jun Young Choi, Ji Eun Park, Dong Hyun Kim, Jin Suk Oh, Tae Geun Kim   +6 more
wiley   +2 more sources

Random Telegraph Noise in 3D NAND Flash Memories [PDF]

Micromachines, 2021
In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport.
Sottocornola Spinelli A., Malavena G., Lacaita A. L., Monzio Compagnoni C.   +3 more
openaire   +3 more sources

Single Event Effects in 3D NAND Flash Memory Cells with Replacement Gate Technology [PDF]

, 2022
We studied the heavy-ion single event effect response of 3D NAND Flash memory cells with charge-trap based replacement gate technology. Error cross sections, threshold voltage shifts, and underlying mechanisms are discussed.
Gerardin S., Beltrami S., Costantino A., Ferlet-Cavrois V., Bagatin M., Paccagnella A., Pesce A.   +6 more
core   +1 more source

Hydrogen Source and Diffusion Path for Poly-Si Channel Passivation in Xtacking 3D NAND Flash Memory

IEEE Journal of the Electron Devices Society, 2020
Poly-Si channels need well passivated by using hydrogen passivation process in 3D NAND flash memories for better poly-Si quality with low trap density.
Xinshuai Shen, Zhiliang Xia, Tao Yang, Lei Liu, Jinwen Dong, Wenxi Zhou, Chunlong Li, Zongliang Huo   +7 more
doaj   +1 more source

A Novel Program Suspend Scheme for Improving the Reliability of 3D NAND Flash Memory

IEEE Journal of the Electron Devices Society, 2022
Experimental results indicate that the conventional program suspend scheme in 3D NAND flash memory chip can generate unexpected additional read fail bits and reduce the reliability of 3D NAND flash memory. These extra read fail bits are observed when the
Zhichao Du, Zhipeng Dong, Kaikai You, Xinlei Jia, Ye Tian, Yu Wang, Zhaochun Yang, Xiang Fu, Fei Liu, Qi Wang, Lei Jin, Zongliang Huo   +11 more
doaj   +1 more source

3D NAND flash memory based on junction-less a-Si:H channel with high on/off current ratio

AIP Advances, 2022
As the key hardware unit of computing in memory, 3D NAND flash memory has been the focus of the artificial intelligence (AI) era due to its high efficiency in processing massive and diverse data, which is superior to the conventional von-Neumann ...
Xinyue Yu, Zhongyuan Ma, Kangmin Leng, Tong Chen, Wei Li, Kunji Chen, Jun Xu, Ling Xu   +7 more
doaj   +1 more source

EDACs and test integration strategies for NAND flash memories [PDF]

, 2010
Mission-critical applications usually presents several critical issues: the required level of dependability of the whole mission always implies to address different and contrasting dimensions and to evaluate the tradeoffs among them. A mass-memory device
Piazza, R., Stefano Di Carlo, Michele Fabiano, Politecnico Di Torino, Fabiano, Michele, Paolo Prinetto, Prinetto, Paolo Ernesto, Roberto Piazza, Piazza R., Di Carlo, Stefano   +9 more
core   +1 more source

Experimental Investigation of Threshold Voltage Temperature Effect During Cross-Temperature Write–Read Operations in 3-D NAND Flash

IEEE Journal of the Electron Devices Society, 2021
Reading data at a temperature which different from writing can cause a large number of failed bits in 3D NAND Flash memory. In this work, the threshold voltage (Vth) temperature effect of 3D NAND flash memory cell was investigated and a method was ...
Dan Wu, Hailong You, Xiaoguang Wang, Shujing Zhong, Qi Sun   +4 more
doaj   +1 more source

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories [PDF]

, 2012
In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage ...
C. Zambelli, P. Olivo, Indaco, Marco, Olivo P., M. Indaco, BERTOZZI, Davide, Zambelli, C., Di Carlo, Stefano, Olivo, P., Bertozzi D., P. Prinetto, D. Bertozzi, M. Fabiano, ZAMBELLI, Cristian, OLIVO, Piero, Fabiano, Michele, Prinetto, Paolo Ernesto, S. Di Carlo, Bertozzi, D., Zambelli C.   +19 more
core   +1 more source