Results 31 to 40 of about 4,190 (193)

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

IEEE Access, 2021
In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss.
Fei Wang, Yuan Li, Xiaolei Ma, Jiezhi Chen   +3 more
doaj   +1 more source

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability [PDF]

, 2017
To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored.
Mittal, Sparsh, Vetter, Jeffrey, Wang, Rujia   +2 more
core   +3 more sources

Analysis of High-Temperature Data Retention in 3D Floating-Gate nand Flash Memory Arrays

IEEE Journal of the Electron Devices Society, 2023
In this paper, we present a detailed experimental investigation of high-temperature data retention in 3D floating-gate NAND Flash memory arrays. Data reveal that charge detrapping from the cell tunnel oxide and depassivation of traps in the string ...
Gerardo Malavena, Mattia Giulianini, Luca Chiavarone, Alessandro S. Spinelli, Christian Monzio Compagnoni   +4 more
doaj   +1 more source

Survey of storage systems for high-performance computing [PDF]

, 2018
In current supercomputers, storage is typically provided by parallel distributed file systems for hot data and tape archives for cold data. These file systems are often compatible with local file systems due to their use of the POSIX interface and ...
Alforov, Yevhen, Betke, Eugen, Duwe, Kira, Kuhn, Michael, Kunkel, Julian, Ludwig, Thomas, Lüttgau, Jakob   +6 more
core   +1 more source

Adaptive Pulse Programming Scheme for Improving the V_th Distribution and Program Performance in 3D NAND Flash Memory

IEEE Journal of the Electron Devices Society, 2021
For triple-level or quad-level 3D NAND flash memory, narrowing the Vth distribution of each state without influencing page program performance is one of the challenges.
Zhichao Du, Shuang Li, Yu Wang, Xiang Fu, Fei Liu, Qi Wang, Zongliang Huo   +6 more
doaj   +1 more source

Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer

Nanomaterials, 2023
Three-dimensional NAND flash memory with high carrier injection efficiency has been of great interest to computing in memory for its stronger capability to deal with big data than that of conventional von Neumann architecture.
Hongsheng Hu, Zhongyuan Ma, Xinyue Yu, Tong Chen, Chengfeng Zhou, Wei Li, Kunji Chen, Jun Xu, Ling Xu   +8 more
doaj   +1 more source

Investigation of Re-Program Scheme in Charge Trap-Based 3D NAND Flash Memory

IEEE Journal of the Electron Devices Society, 2021
Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND (Shibata et al., 2007, Lee et al., 2018,
Ting Cheng, Jianquan Jia, Lei Jin, Xinlei Jia, Shiyu Xia, Jianwei Lu, Kaiwei Li, Zhe Luo, Da Li, Hongtao Liu, Qiguang Wang, An Zhang, Daohong Yang, Zongliang Huo   +13 more
doaj   +1 more source

Vertical Self-Rectifying Memristive Arrays for Page-Wise Parallel Logic and Arithmetic Processing. [PDF]

Adv Mater
This study proposes a page‐wise logic‐in‐memory architecture realized in a 3D vertical resistvie random‐access memory array of self‐rectifying memristors. By introducing intra‐ and inter‐page logic primitives, the system enables Boolean and arithmetic operations to be executed directly within the memory.
Son K, Cho JM, Shin DH, Kim YR, Ghenzi N, Cheong S, Kim BS, Lee JK, Kim S, Choi W, Lee SH, Han J, Hwang CS.   +12 more
europepmc   +2 more sources

Optimization and evaluation of variability in the programming window of a flash cell with molecular metal-oxide storage [PDF]

, 2014
We report a modeling study of a conceptual nonvolatile memory cell based on inorganic molecular metal-oxide clusters as a storage media embedded in the gate dielectric of a MOSFET.
Asenov, Asen, Busche, Christoph, Cronin, Leroy, Georgiev, Vihar P., Markov, Stanislav, Vila-Nadal, Laia   +5 more
core   +3 more sources

Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory

IEEE Journal of the Electron Devices Society, 2020
As the 3D NAND technology developing toward more and more stack layers, it is essential to shrink the gate length (Lg) and inter-gate space (Ls). However, one of key concerns of scaling Lg/Ls 3D NAND flash is post-cycling data retention characteristics ...
Xinlei Jia, Lei Jin, Wei Hou, Zhiyu Wang, Songmin Jiang, Kaiwei Li, Dejia Huang, Hongtao Liu, Wenzhe Wei, Jianwei Lu, An Zhang, Zongliang Huo   +11 more
doaj   +1 more source