Results 11 to 20 of about 36,961 (291)
Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay
EURASIP Journal on Wireless Communications and Networking, 2005 The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop.
Nasir Qassim
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Understanding of the Coherent Demodulation with Phase-Locked Loop
MATEC Web of Conferences, 2018 The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way.
Zhai Bingcong
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Design of novel hybrid - digitally controlled oscillator for ADPLL
Memories - Materials, Devices, Circuits and Systems, 2023 Digitally Controlled Oscillators (DCOs) are an integral part of All Digital Phase Locked Loops (ADPLLs). It is used to generate output frequency corresponding to the applied digital input.
Mohd Ziauddin Jahangir +1 more
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Synchronized State in Networks of Digital Phase-Locked Loops [PDF]
, 2010 International audienceClock distribution networks of synchronized oscillators are an alternative approach to classical tree-like clock distribution methods.
Akre, Jean-Michel +3 more
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A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
Applied Sciences, 2019 In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs).
Chenggang Yan, Chen Hu, Jianhui Wu
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Modelling of 3-Phase p-q Theory-Based Dynamic Load for Real-Time Simulation
IEEE Open Access Journal of Power and Energy, 2023 This article proposes a new method of modelling dynamic loads based on instantaneous p-q theory, to be employed in large powers system network simulations in a digital real-time environment.
Karthik Rajashekaraiah +3 more
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Energies, 2020 The interconnection of new generating and storing devices to the power grid imposes the necessity of synchronizing, so the power flow can be manipulated and distributed.
Luis Ibarra +3 more
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Hold-in, pull-in, and lock-in ranges of PLL circuits: rigorous mathematical definitions and limitations of classical theory [PDF]
, 2015 The terms hold-in, pull-in (capture), and lock-in ranges are widely used by engineers for the concepts of frequency deviation ranges within which PLL-based circuits can achieve lock under various additional conditions. Usually only non-strict definitions
Kuznetsov, N. V. +3 more
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An Adaptive Phase Alignment Algorithm for Cartesian Feedback Loops [PDF]
, 2010 An adaptive algorithm to correct phase misalignments in Cartesian feedback linearization loops for power amplifiers has been presented. It yields an error smaller than 0.035 rad between forward and feedback loop signals once convergence is reached ...
Gimeno Martín, Alejandro +2 more
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Single-Phase PLL Based on an Adaptive Notch Filter
Advances in Electrical and Electronic Engineering, 2020 Single-Phase Phase-Locked Loops (PLL) have become a crucial component of grid-tied power converters. PLL accuracy and fast response are important for control and protection purposes, especially in the presence of voltage harmonics and frequency ...
Luciano Emilio Belandria, Joan Bergas
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