An Efficient FeFET-Based Compute-In-Memory Macro Readout Inspired by the 3T Pixel Array Cell
This paper proposes an In-Memory Computing (IMC) FeFET-based macro for ÁI acceleration. Central to this concept is the adoption of a novel readout circuit inspired by the proven efficiency of the 3T pixel array cell. Designed in 28 nm GF technology, this
Laleni, Nellie, Kämpfe, Thomas
core +1 more source
Time-Domain Simulation and Optimization of the Memory Window for HZO-Based FeFETs Using the NLS Model. [PDF]
Han S, Lü W, Liang Y, Dai T.
europepmc +1 more source
Amphibian-inspired neuromorphic dynamic vision systems based on ferroelectric field-effect transistor. [PDF]
Zhai Y +9 more
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Stable Analog Weight Programming in Single-Crystalline van der Waals Ferroelectric Transistors for Reliable Computing-in-Memory. [PDF]
Li M +18 more
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Light polarization-based electro-optic memory. [PDF]
Wan Q +9 more
europepmc +1 more source
Towards Artificial Intelligence Hardware With 3D Integrated Ferroelectric Transistors. [PDF]
Seok H, Kim G, Son S, Choi H, Kim T.
europepmc +1 more source
Automated, physics-guided AI framework for asymmetry-aware ferroelectric compact models. [PDF]
Kim J +8 more
europepmc +1 more source
TiO<sub>2</sub> nanolayer-assisted top-interface engineering for disturbance-free FeFETs: a blueprint for future van der Waals memory. [PDF]
Kang H +11 more
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Endurance Paradox in Hafnium-Oxide-Based Silicon-Channel Ferroelectric Transistors. [PDF]
Das A +14 more
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Nanogate ferroelectric transistors with ultralow operation voltage of 0.6 V. [PDF]
Meng D +5 more
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