Results 61 to 70 of about 553 (192)
S.42-51With the discovery of ferroelectric hafnium oxide (FE-HfO2), the ferroelectric field effect transistor (FeFET), a long-term contender for non-volatile data storage, has finally managed to scale to the 2x nm technology node. Here for the first time,
Flachowsky, S. +8 more
core +1 more source
Neuromorphic Near‐Sensor and In‐Sensor Computing Enabled by Next‐Generation Material‐Based Sensors
This Review presents a structural framework that classifies neuromorphic sensing into near‐sensor and in‐sensor architectures, clarifying physical coupling between sensing and computation. The framework connects neural and synaptic device functions with recent advances in optical, mechanical, and chemical sensing, compares energy consumption and ...
Su Yeon Jung +7 more
wiley +1 more source
Ising machines are emerging as specialized hardware solvers for computationally hard optimization problems. This review examines five major platforms—digital CMOS, analog CMOS, emerging devices, coherent optics, and quantum systems—highlighting physics‐rooted advantages and shared bottlenecks in scalability and connectivity.
Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim
wiley +1 more source
Ferroelectric polarization charge in doped-HfO2 such as HfZrOx (HZO) has a high surface density (~1014 cm-2) compared to the channel carrier (~1013 cm-2), thereby, ferroelectric polarization induces high electric field near the channel ...
Song-Hyeon Kuk +5 more
doaj +1 more source
Robust and Compatible Ferroelectric Memories with Polycrystalline TiO2 Channel for 3D Integration
Robust and monolithic 3D compatible ferroelectric memories are realized using the polycrystalline TiO2 channel‐based FeFET. The review covers physical mechanisms of the TiO2 channel FeFET, quantitative benchmarking, and advanced planar/vertical architectures for monolithic 3D integration based on HfO2‐TiO2 gate stack, offering a roadmap for reliable ...
Xujin Song +10 more
wiley +1 more source
The von Neumann architecture faces severe bottlenecks in energy efficiency. Computing-in-Memory (CiM) addresses this by performing computations within memory arrays, yet analog CiM solutions suffer from precision loss and high overhead from analog-to-digital converters and digital-to-analog converters (ADCs/DACs).
Chengyu He +5 more
openaire +1 more source
Emerging Memory and Device Technologies for Hardware‐Accelerated Model Training and Inference
This review investigates the suitability of various emerging memory technologies as compute‐in‐memory hardware for artificial intelligence (AI) applications. Distinct requirements for training‐ and inference‐centric computing are discussed, spanning device physics, materials, and system integration.
Yoonho Cho +6 more
wiley +1 more source
First demonstration of in-memory computing crossbar using multi-level Cell FeFET
Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges.
Taha Soliman +8 more
doaj +1 more source
Analog Weight Update Rule in Ferroelectric Hafnia, Using picoJoule Programming Pulses
Resistive, ferroelectric synaptic weights based on BEOL‐compatible hafnia/zirconia nanolaminates are fabricated. Lateral downscaling the devices below 10 µm2 enables 20 ns programming with electrical pulses, dissipating ≤ 3 pJ. Experimental results show that final conductance state is set by pulse amplitude, and is largely independent of the initial ...
Alexandre Baigol +7 more
wiley +1 more source
This article presents the world's first demonstration of a neural network SPICE integration platform (NSIP) for simulating synaptic weights in HfZrO (HZO)‐based ferroelectric field‐effect transistor (FeFET) crossbar arrays tailored for neuromorphic ...
Juhwan Park +3 more
doaj +1 more source

