Results 191 to 200 of about 81,608 (254)

Gate-All-Around Nanopore Osmotic Power Generators

ACS Nano
Nanofluidic channels in a membrane represent a promising avenue for harnessing blue energy from salinity gradients, relying on permselectivity as a pivotal characteristic crucial for inducing electricity through diffusive ion transport. Surface charge emerges as a central player in the osmotic energy conversion process, emphasizing the critical ...
Makusu Tsutsui, Wei-Lun Hsu, Denis Garoli, Iat Wai Leong, Kazumichi Yokota, Hirofumi Daiguji, Tomoji Kawai   +6 more
openaire   +3 more sources

Germanium Gate-All-Around FETs on SOI

ECS Meeting Abstracts, 2012
Abstract not Available.
Hung-Chih Chang, S.-H Hsu, C.-L Chu, W.-H Tu, Y.-T Chen, P.-J Sung, G.-Li Luo, C. W. Liu   +7 more
openaire   +1 more source

Journey of MOSFET from Planar to Gate All Around: A Review

Recent Patents on Nanotechnology, 2022
: With the continuous miniaturization in device dimension to reach the expectation raised by semiconductor users, the shape and size of the MOSFET are changing periodically. The journey started in the year 1960, reached the milestone, and still going on to create history.
Umakanta Nanda, Krutideepa Bhol, Biswajit Jena   +2 more
openaire   +2 more sources

Silicon-on-insulator 'gate-all-around device'

International Technical Digest on Electron Devices, 2002
Describes the process fabrication and the electrical characteristics of an SOI (silicon-on-insulator) MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it. Device fabrication is simple and necessitates only a single additional mask and etch step, compared to standard SOI processing.
J.P. Colinge, M.H. Gao, A. Romano-Rodriguez, H. Maes, C. Claeys   +4 more
openaire   +1 more source

(Invited) Gate-All-Around Ge FETs

ECS Meeting Abstracts, 2014
Abstract- High performance Ge inversion (INV) and junctionless (JL) GAAFETs are demonstrated. The (111) sidewall-enhanced Ge GAA nFETs show 2x enhanced Ion of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls and subthreshold characteristics of 94 mV/dec. The JL Ge GAA pFETs with fin width (Wfin) down to 27 nm and
C. W. Liu, Yen-Ting Chen, Shu-Han Hsu
openaire   +1 more source

Modeling of Nanoscale Gate-All-Around MOSFETs

IEEE Electron Device Letters, 2004
We present a compact physics-based model for the nanoscale gate-all-around MOSFET working in the ballistic limit. The current through the device is obtained by means of the Landauer approach, being the barrier height the key parameter in the model. The exact solution of the Poisson's equation is obtained in order to deal with all the operation regions ...
D. Jimenez, J.J. Saenz, B. Iniguez, J. Sune, L.F. Marsal, J. Pallares   +5 more
openaire   +1 more source

SiGe Gate-All-around Nanosheet Reliability

2022 IEEE International Reliability Physics Symposium (IRPS), 2022
Huimei Zhou, Miaomiao Wang 0006, Ruqiang Bao, Curtis Durfee, Liqiao Qin, Jingyun Zhang   +5 more
openaire   +1 more source

Gate-all-around technology: Taking advantage of ballistic transport?

Solid-State Electronics, 2009
Abstract This work presents an experimental study in order to evaluate the quality of transport in the most advanced state-of-the-art gate-all-around devices in term of performances. Experiments have been done on silicon channel devices with metal/high-k gate all-round stack at aggressive dimensions (L × W × TSi = 25nm × 20 nm × 10nm).
J.L., Huguenin, Bidal, G., Denorme, S., Fleury, D., Loubet, N., Pouydebasque, A., Perreau, P., Leverd, F., Barnola, S., Beneyton, R., Orlando, B., Gouraud, P., Salvetat, T., Clement, L., Monfray, S., Ghibaudo, G., Boeuf, F., Skotnicki, T.   +17 more
openaire   +1 more source

Analysis of back gate and gate all around CNTFET structure

Proceedings of the International Conference & Workshop on Emerging Trends in Technology, 2011
Current CMOS technology has put forth many challenges like scaling issues, short channel effects, etc. The various remedies proposed to solve these include the use of strained silicon, silicon on insulator structure, double, tri-gate and Gate All around structures for CMOS, use of Graphene and Carbon Nanotube (CNT) devices, quantum cellular automata ...
M. R. Tambekar, S. R. Nade, A. Gajarushi
openaire   +1 more source

Characterization and reliability of III-V gate-all-around MOSFETs

2015 IEEE International Reliability Physics Symposium, 2015
InGaAs is a promising channel material for high performance CMOS logic circuits due to its large electron injection velocity. InGaAs Gate-All-Around (GAA) MOSFETs have been demonstrated; these transistors offer large drive current and excellent immunity to short channel effects (SCE).
Mengwei Si, SangHoon Shin, Nathan J. Conrad, Jiangjiang Gu, Jingyun Zhang, Muhammad Ashraful Alam, Peide D. Ye   +6 more
openaire   +1 more source