Results 101 to 110 of about 4,617 (218)

Surface-Potential-Based Drain Current Model of Gate-All-Around Tunneling FETs

IEEE Journal of the Electron Devices Society
A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated.
Zhanhang Chen, Haoliang Shan, Ziyi Ding, Xia Wu, Xiaolin Cen, Xiaoyu Ma, Wanling Deng, Junkai Huang   +7 more
doaj   +1 more source

Effect of Metal Gate Granularity Induced Random Fluctuations on Si Gate-All-Around Nanowire MOSFET 6-T SRAM Cell Stability [PDF]

, 2016
In this paper, we present a variability-aware 3-D mixed-mode device simulation study of Si Gate-All-Around (GAA) Nanowire MOSFET (NWFET) based 6-T SRAM bit-cell stability and performance considering metal-gate granularity (MGG) induced ...
Nayak, Kaushik, Gundapaneni, S, Bajaj, M, Rao, V R, Nayak, K   +4 more
core   +1 more source

Spatial Sensitivity of Silicon GAA Nanowire FETs Under Line Edge Roughness Variations

IEEE Journal of the Electron Devices Society, 2018
Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However, this spatial information is paramount for the industry and academia to improve the design of variability-resistant ...
Guillermo Indalecio, Antonio J. Garcia-Loureiro, Muhammad A. Elmessary, Karol Kalna, Natalia Seoane   +4 more
doaj   +1 more source

Analitical modeling for square gate-all-around MOSFETs [PDF]

, 2014
Two analytical models for square Gate All Around (GAA) MOSFETs has been introduced. The first part of this report include a quantum viewpoint and this first work has been published, while the second part approach a classical developed.
Moreno Pérez, Enrique
core   +1 more source

Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime

IEEE Open Journal of Nanotechnology
This research focuses on a quantum model created using an entirely novel nanosheet FET. The standard model describes the performance of a Gate-all-around (GAA) Junction-less (JL) nanosheet device with a gate dielectric of SiO2 and HfO2, each having a ...
Asisa Kumar Panigrahy, Sudheer Hanumanthakari, Shridhar B. Devamane, Shruti Bhargava Choubey, M. Prasad, D. Somasundaram, N. Kumareshan, N. Arun Vignesh, Gnanasaravanan Subramaniam, Durga Prakash M, Raghunandan Swain   +10 more
doaj   +1 more source

Performance investigation of 1T1R memory cell using GAA MBC-FET technology

Memories - Materials, Devices, Circuits and Systems
The ultimate advancement beyond FinFET technology is the Gate-All-Around (GAA) Multi-Bridge-Channel FET (MBCFET) technology. GAA MBCFET features vertically stacked multiple channels, a departure from single-channel designs, thereby enhancing overall ...
Rinku Rani Das, Devenderpal Singh, Alex James   +2 more
doaj   +1 more source

Low-Power Energy-Efficient Hetero-Dielectric Gate-All-Around MOSFETs: Enablers for Sustainable Smart City Technology

Energies
In the context of increasing digitalization and the emergence of applications such as smart cities, embedded devices are becoming ever more pervasive, mobile, and ubiquitous.
Ram Devi, Gurpurneet Kaur, Ameeta Seehra, Munish Rattan, Geetika Aggarwal, Michael Short   +5 more
doaj   +1 more source

A Compact Model for Program Operation of Gate-All-Around Barrier-Engineered Charge-Trapping NAND Flash Memory in the FN-Tunneling Regime

IEEE Journal of the Electron Devices Society
We introduce a compact model for characterizing the transient program operation of Gate-All-Around (GAA) Barrier-Engineered charge-trapping NAND flash (BE-CTNF) memory, especially in the FN-tunneling regime.
Haechan Choi, Hyungcheol Shin
doaj   +1 more source

Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor [PDF]

Journal of Optoelectronical Nanostructures, 2019
In this paper, we have presented a heterojunction gate all around nanowiretunneling field effect transistor (GAA NW TFET) and have explained its characteristicsin details.
Mahsa Roohy, Reza Hosseini
doaj  

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

IEEE Journal of the Electron Devices Society
Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect ...
Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh   +5 more
doaj   +1 more source