Results 101 to 110 of about 4,456 (178)

Stacked Nanosheet Gate-All-Around Morphotropic Phase Boundary Field-Effect Transistors. [PDF]

Adv Sci (Weinh)
Kim S, Kim HM, Kwon KR, Kwon D.
europepmc   +1 more source

Performance Assessment of Ultrascaled Vacuum Gate Dielectric MoS₂ Field-Effect Transistors: Avoiding Oxide Instabilities in Radiation Environments. [PDF]

Micromachines (Basel)
Tamersit K, Kouzou A, Rodriguez J, Abdelrahem M.   +3 more
europepmc   +1 more source

Dielectric and Gate Metal Engineering for Threshold Voltage Modulation in Enhancement Mode Monolayer MoS₂ Field Effect Transistors. [PDF]

Adv Mater
Liu L, Yan H, Loh L, Paul KK, Sarkar S, Biswas D, Lee TL, Taniguchi T, Watanabe K, Chhowalla M, Wang Y.   +10 more
europepmc   +1 more source

Challenges and prospects of 2D electronics for future monolithic complementary field-effect transistors. [PDF]

Nat Commun
Islam MM, Cho Y, Sen A, Bisht P, Shim J, Oh JO, Park G, Rossi A, Lee H, Jiang L, Coletti C, Park BI, Chae H, Shin S, Park H, Kim S.   +15 more
europepmc   +1 more source

Improving the Performance of Arsenene Nanoribbon Gate-All-Around Tunnel Field-Effect Transistors Using H Defects. [PDF]

Nanomaterials (Basel)
Song S, Qin L, Wang Z, Lyu J, Gong J, Yang S.   +5 more
europepmc   +1 more source

Correction: Hsieh et al. Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits. <i>Micromachines</i> 2020, <i>11</i>, 741. [PDF]

Micromachines (Basel)
Hsieh TY, Hsieh PY, Yang CC, Shen CH, Shieh JM, Yeh WK, Wu MC.   +6 more
europepmc   +1 more source

Hf/Zr Superlattice-Based High-κ Gate Dielectrics with Dipole Layer Engineering for Advanced CMOS. [PDF]

ACS Nano
Song T, Kang S, Kuo YH, Chen J, Fernandes L, Afroze N, Tian M, Baac HW, Shin C, Khan AI.   +9 more
europepmc   +1 more source

High-density three-dimensional integration of dynamic random-access memory using vertical dual-gate IGZO TFTs. [PDF]

Nat Commun
Liao F, Zhu Z, Li Z, Yang G, Liu M, Chen K, Lu W, Wu Z, Zhang X, Mao N, Kang BM, Shi J, Wu XS, Jin M, Liu C, Zhang J, Yu Y, Wang GL, Lu C, Yue J, Wang L, Wang J, Geng D, Lu N, Zhao C, Nathan A, Li L, Liu M.   +27 more
europepmc   +1 more source

Advancing 2D CMOS electronics with high-performance p-type transistors. [PDF]

Nat Commun
Jiang J, Zheng X, Liu Y, Li LJ, Xu L, Kong J, Peng LM.   +6 more
europepmc   +1 more source

Impact of Contact Gating on Scaling of Monolayer 2D Transistors Using a Symmetric Dual-Gate Structure. [PDF]

ACS Nano
Ravel VM, Evans SR, Holmes SK, Doherty JL, Rahman MS, Roy T, Franklin AD.   +6 more
europepmc   +1 more source