Results 111 to 120 of about 4,617 (218)

A Review of Reliability in Gate-All-Around Nanosheet Devices [PDF]

The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET ...
Miaomiao Wang
core   +1 more source

Analytical subthreshold swing model of junctionless elliptic gate-all-around (GAA) FET

AIMS Electronics and Electrical Engineering
<p>An analytical subthreshold swing (SS) model has been presented to determine the SS of an elliptic junctionless gate-all-around field-effect transistor (GAA FET). The analysis of a GAA FET with an elliptic cross-section is essential because it is difficult to manufacture a GAA FET with an accurate circular cross-section during the process.
openaire   +2 more sources

A Gate-All-Around Floating-Gate Memory Device with Triangular-Shaped Poly-Si Nanowire Channels [PDF]

, 2013
[[abstract]]A novel gate-all-around (GAA) poly-Si floating-gate (FG) memory device with triangular nanowire (NW) channels was fabricated and characterized in this work.
蔡宗叡;TSAI,JUNG-RUEY*;李克慧Lee, Ko-Hui Lee;林鴻志Lin, Horng-Chih;黃調元;Huang, Tiao-Yuan, 蔡宗叡(TSAI, JUNG-RUEY)*、李克慧(Lee, Ko-Hui Lee)、林鴻志(Lin, Horng-Chih)、黃調元(Huang, Tiao-Yuan), 蔡宗叡;TSAI, JUNG-RUEY;李克慧;Lee, Ko-Hui Lee;林鴻志;Lin, Horng-Chih;黃調元;Huang, Tiao-Yuan   +2 more
core  

3D Nanoscale Imaging of Semiconductor Films for GAA (Gate All Around) Device Development

Microscopy and Microanalysis, 2022
Pritesh Parikh, Darshan Jaware, Jiangtao Zhu   +2 more
openaire   +1 more source

3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography. [PDF]

Nat Commun
Karapetyan S, Zeltmann SE, Wilk G, Chen TK, Hou VD, Muller DA.   +5 more
europepmc   +1 more source

Fabrication of silicon nano wires and gate-all-around MOS devices [PDF]

The invention relates to methods for manufacturing semiconductor devices. Processes are disclosed for implementing suspended single crystal silicon nano wires (NWs) using a combination of anisotropic and isotropic etches and spacer creation for sidewall ...
Bouvet, Didier, Ionescu, Mihai A, Moselund, Kirsten   +2 more
core  

Scaling nanoribbon transistors with monolayer transition metal dichalcogenides. [PDF]

Nat Nanotechnol
Peña T, Persson AEO, Krayev A, Friðriksdóttir Á, Su H, Lee YM, Song YS, Neilson K, Zhang Z, Hoang AT, Yang JA, Hoang L, Wang SX, Mannix AJ, McIntyre PC, Pop E.   +15 more
europepmc   +1 more source

Large-scale gate-all-around MoS₂ transistor array through lossless monolithic 3D integration. [PDF]

Natl Sci Rev
Chen C, Chen K, Zhao H, Lu S, Shang J, Jiang H, Gao L, He X, Jiang S, Chen Z, Zhang Z, Zhang X, Zhang Y.   +12 more
europepmc   +1 more source

Design and performance analysis of a vertically stacked gate-all-around nanosheet FET with embedded nanocavity for biosensing applications. [PDF]

Sci Rep
Prasanna RL, Karumuri SR, Sreenivasulu VB, Kondaveeti GS.   +3 more
europepmc   +1 more source

Development and Performance Analysis of High-K Spacer-Induced Strained Si/SiGe Channel-Based Gate All Around FET for Thermal Effects. [PDF]

Nanomaterials (Basel)
Yugender P, Singh S, Kumar K, Dhar RS, Seteikin AY, Banerjee A, Samusev IG.   +6 more
europepmc   +1 more source