Results 131 to 140 of about 4,456 (178)

Lateral gate-all-around (GAA) poly-Si transistors

2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207), 2002
High performance near-single grain poly-Si lateral gate-all-around (GAA) MOS transistors have been demonstrated. A high I/sub ON//I/sub OFF/ ratio of 10/sup 8/ and nearly ideal subthreshold slope of 67 mV/dec were achieved. These devices were fabricated using a novel technique for crystallization of a-Si.
P. Kalavade, K.C. Saraswat
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ESD characterization of gate-all-around (GAA) Si nanowire devices

2015 IEEE International Electron Devices Meeting (IEDM), 2015
In CMOS scaling roadmap, gate-all-around (GAA) nanowire (NW) is a promising candidate in sub-10nm nodes. However, newly introduced process options in GAA NW technologies can result in significant impacts on intrinsic ESD performance. In this work, ESD protection devices in GAA NW architecture are studied and the corresponding 3D TCAD simulations bring ...
S.-H. Chen, D. Linten, G. Hellings, A. Veloso, M. Scholz, R. Boschke, G. Groeseneken, N. Collaert, A. Thean   +8 more
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Investigation on cylindrical gate-all-around (GAA) tunnel FETS scaling

2017 IEEE 30th International Conference on Microelectronics (MIEL), 2017
The present work deals with the study and investigation on the GAA Tunnel FET electrical parameters under varying physical conditions, especially, channel thickness t si and length, as well as oxide thickness t ox . Moreover, the effect of the channel doping concentration and the gate work function Φ m .
M. Kessi, A. Benfdila, A. Lakhlef
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Scatterometry for gate all around (GAA) technology enablement (Conference Presentation)

Metrology, Inspection, and Process Control for Microlithography XXXII, 2018
Future of logic silicon extension lies at the heart of gate all around developments (1). Due to the increasing limitations in further FinFET flow extension, teams around the globe are researching with vertical and horizontal nanowires flavors. Horizontal NW are of great interest due to their integration similarity to the existing FinFET integration ...
Anne-Laure Charley, Hans Mertens, Naoto Horiguchi, Philippe Leray, Nivea Figueiró, Matthew Sendelbach, Roy Koret, Avron Ger, Shay Wolfling   +8 more
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vfTLP characteristics of ESD devices in Si gate-all-around (GAA) nanowires

2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2016
Beyond 7nm nodes, gate-all-around (GAA) nanowire (NW) is a promising device architecture. However, new architecture can result in intrinsic ESD performance degradation. In this work, we study vfTLP characteristics of GAA ESD devices. Transient analysis bring an in-depth understanding on physical failure mechanism of GAA devices during CDM ESD events.
Shih-Hung Chen, Dimitri Linten, Geert Hellings, Anabela Veloso, Mirko Scholz, Roman Boschke, Guido Groeseneken, Nadine Collaert, Naoto Horiguchi, Aaron Thean   +9 more
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Analytical Quantum Model for Germanium Channel Gate-All-Around (GAA) MOSFET

Journal of Nano Research, 2019
The paper proposes analytical model for Gate-All-Around Metal Oxide Semiconductor Field Effect Transistor (GAA-MOSFET) for germanium channel including quantum mechanical effects. It is achieved by solving coupled Schrodinger-Poisson’s equation using variational approach. The proposed model takes quantum confinement effects to obtain charge centroid and
P. Vimala, N.R. Nithin Kumar
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Sub-20nm GaAs-based Cylindrical Gate-All-Around FETs for Improved Performance

2021 2nd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST), 2021
In this work, a cylindrical gate-all-around field-effect transistor (CGAA FET) has been implemented using gallium arsenide (GaAs) as the channel material instead of the conventional silicon material. The investigations based on the simulations using the Atlas tool of the Silvaco TCAD software prompts out that the GaAs-based CGAA FET is capable of ...
Prince Joy Chakraborty, Md. Mossabbarul Islam, Razu Ahamed, Md. Iqbal Bahar Chowdhury   +3 more
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Modelling and simulation of Si and InAs gate all around (GAA) nanowire transistors

2015 Annual IEEE India Conference (INDICON), 2015
Owing to the large increase number of transistors in the CMOS logic due to the unending demand for increase in speed of electronic devices and also low power consumptions, it is becoming difficult to incorporate all the small scaled transistors onto one single plane.
Neel Chatterjee, Sujata Pandey
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Novel Architecture in Gate-All-Around (GAA) MOSFET with High-k Dielectric for Biomolecule Detection

2021
In this chapter, an investigative unique structure of reconfigurable nanowire-based GAA-MOSFET has been developed, which works as biosensor to notice biomolecules such as DNA, protein, cell, enzyme, etc. It performs as both n-type and p-type depending on the polarization of the applied biasing because of its reconfigurable behavior.
Bhol, Krutideepa, Jena, Biswajit, Nanda, Umakanta, Tayal, Shubham, Jain, Amit Kumar   +4 more
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(Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

ECS Meeting Abstracts, 2019
This paper addresses the opportunities and challenges of wet and dry etches in the integration of gate-all-around (GAA) device, which is emerging as a promising solution to replace FinFET [1-3]. For the GAA device fabrication, a quintessential challenge is an isotropic etching of dielectrics, semiconductors, and metals with high selectivity to the ...
Yusuke Oniki, Efraín Altamirano-Sánchez, Frank Holsteyns   +2 more
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