Results 21 to 30 of about 4,617 (218)

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

IEEE Access, 2023
With transistors scaling down to 3 nm node and beyond, short channel effect (SCE) as well as power consumption dissipation present immense challenges for further scaling down of the transistor.
Laixiang Qin, Chunlai Li, Yiqun Wei, Guoqing Hu, Jingbiao Chen, Yi Li, Caixia Du, Zhangwei Xu, Xiumei Wang, Jin He   +9 more
doaj   +1 more source

NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants [PDF]

, 2012
We have carried out 3D Non-Equilibrium Green Function simulations of ajunctionlessgate-all-around n-type silicon nanowiretransistor of 4.2 × 4.2 nm2 cross-section. We model the dopants in a fully atomistic way.
Brown, A., Asenov, A., A. Martinez, Aldegunde, M., M. Aldegunde, A. Asenov, Martinez, A., Antonio Martinez Muniz, A.R. Brown, Roy, S., S. Roy   +10 more
core   +1 more source

A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines, 2020
Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy ...
Yannan Zhang, Ke Han, and Jiawei Li
doaj   +1 more source

Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets

Micromachines, 2022
A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring
Kun Chen, Jingwen Yang, Tao Liu, Dawei Wang, Min Xu, Chunlei Wu, Chen Wang, Saisheng Xu, David Wei Zhang, Wenchao Liu   +9 more
doaj   +1 more source

Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET

IEEE Access, 2022
Nous avons démontré un transistor à effet de champ (TFET) à effet de champ tunnel (NC) à capacité négative (GAA) à grille tout autour du nanofil basé sur l'hétérostructure GaAs/InN en utilisant la simulation TCAD. Dans l'empilement de grille, nous avons proposé une tricouche HfO2/TiO2/HfO2 comme diélectrique à K élevé et de l'oxyde de hafnium et de ...
Abdullah Al Mamun Mazumder, Kamal Hosen, Md. Sherajul Islam, Jeongwon Park   +3 more
openaire   +2 more sources

Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs

Nanomaterials, 2021
A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology.
Jie Gu, Qingzhu Zhang, Zhenhua Wu, Jiaxin Yao, Zhaohao Zhang, Xiaohui Zhu, Guilei Wang, Junjie Li, Yongkui Zhang, Yuwei Cai, Renren Xu, Gaobo Xu, Qiuxia Xu, Huaxiang Yin, Jun Luo, Wenwu Wang, Tianchun Ye   +16 more
doaj   +1 more source

Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology [PDF]

, 2021
An optimization study of silicon gate-all-around (GAA) devices based on technology computer-aided design tools is presented in this paper. GAA technology guidelines and solutions are provided for low power applications in the 5 nm CMOS technology node ...
Gundu, Anil Kumar, Kursun, Volkan, Anil Kumar Gundu, Volkan Kursun   +3 more
core   +1 more source

Reliability Analysis Of Gate-All-Around Floating Gate (GAA-FG) With Variable Oxide Thickness For Flash Memory Cell [PDF]

, 2020
In this work, a concept of tunnel barrier engineering using Variable Oxide Thickness (VARIOT) of low-k/high-k stack is implemented in Gate-All-Around Floating Gate (GAA-FG) memory cell to reduce P/E operational voltage, improve the efficiency of data ...
Farah Hamid, Tan, M. L. P., Hamzah, A., Ismail, R., M. L. Peng Tan, Hamid, F., Soin, N., N. Ezaila Alias, Zaharah Johari, Norhayati Soin, Afiq Hamzah, Razali Ismail, Alias, N. E., Johari, Z.   +13 more
core   +1 more source

Analog and RF performance optimization for gate all around tunnel FET using broken-gap material

Scientific Reports, 2022
Many times, the fabricated cylindrical gate-all-around tunnel FET (GAA TFET) has an uneven radius due to several etching and deposition processes involved while fabricating the device, which show notable variations in the performance of the device.
Pankaj Kumar, Kalyan Koley, Bhubon C. Mech, Ashish Maurya, Subindu Kumar   +4 more
doaj   +1 more source

Nanodevices Tend to Be Round

Micromachines, 2021
Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle ...
Georges Pananakakis, Gérard Ghibaudo, Sorin Cristoloveanu   +2 more
doaj   +1 more source