Results 61 to 70 of about 85,724 (295)

Complementary Field Effect Transistor (CFET) for the 2-nm Technology Node: A Review From Device to Circuit Perspectives

IEEE Journal of the Electron Devices Society
The relentless advancement of the semiconductor industry continues to be fueled by the pursuit of enhanced transistor performance. As CMOS technology undergoes aggressive scaling to enable higher integration densities in modern integrated circuits (ICs),
J. Ajayan, Vakkalakula Bharath Sreenivasulu, Amit Krishna Dwivedi, Shubham Tayal   +3 more
doaj   +1 more source

Does Long‐Term Lower Extremity Strength Training in Adults With Knee Osteoarthritis and Varus Alignment Reduce Knee Joint Loading During Gait?

Arthritis Care &Research, EarlyView.
Objective We examined whether 18 months of strength training in individuals with knee varus alignment and medial tibiofemoral osteoarthritis (OA) reduced knee joint loads during walking compared to an attention control group. Methods This study was a secondary analysis of a randomized clinical trial that compared the effects of strength training to a ...
Stephen P. Messier, Matthew N. Vigliotti, Paige E. Rice, Brian Pietrosimone, Shannon L. Mihalko, Edward H. Ip, Richard F. Loeser, David J. Hunter, Ali Guermazi, Ryan Hill, Santiago Saldana, Kim L. Bennell, Paul DeVita   +12 more
wiley   +1 more source

Depletion isolation effect in Vertical MOSFETS during transition from partial to fully depleted operation [PDF]

, 2006
A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm.
Ashburn, P., Gili, E., Hakim, M.M.A., Uchino, T., Hall, S., de Groot, C. H.   +5 more
core  

Analytical subthreshold channel potential model of asymmetric gate underlap gate-all-around MOSFET [PDF]

, 2010
In this paper an analytic subthreshold potential model for undoped cylindrical gate-all-around (GAA) MOSFET with asymmetric gate underlap is developed.
Zhang, Lining, He, Frank, Guo, Xinjie, Zhang, Chenfei, Chan, Mansun, Wang, Shaodi   +5 more
core   +1 more source

All‐in‐One Analog AI Hardware: On‐Chip Training and Inference with Conductive‐Metal‐Oxide/HfOx ReRAM Devices

Advanced Functional Materials, EarlyView.
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone, Victoria Clerico, Wooseok Choi, Tommaso Stecconi, Folkert Horst, Laura Bégon‐Lours, Matteo Galetta, Antonio La Porta, Nikhil Garg, Fabien Alibart, Bert Jan Offrein, Valeria Bragaglia   +11 more
wiley   +1 more source

The Fabrication and Simulation of a High Performance SOI Device with Pseudo-Gate-All-Around [PDF]

, 2007
In this thesis, compared to the conventional pseudo gate all around SOI MOSFET, a similar device is successfully implemented already. This three dimension structure illustrate a pseudo gate all around SOI MOSFET which contains at least four advantages as
Chen, Ho-Ting
core  

High threshold voltage matching performance on gate-all-around MOSFET [PDF]

, 2007
International audienceFor the first time, threshold voltage matching was measured on multiple gate transistors, and particularly on Gate-All-Around transistors (GAA) with both doped and undoped channels. Good matching performance is demonstrated on doped
Harrison, S., Coronel, P., Pouydebasque, A., Cathignol, A., Cerrutti, R., Ghibaudo, G., Cros, A., Rochereau, K., Skotnicki, T.   +8 more
core   +1 more source

Printed Integrated Logic Circuits Based on Chitosan‐Gated Organic Transistors for Future Edible Systems

Advanced Functional Materials, EarlyView.
Edible electronics needs integrated logic circuits for computation and control. This work presents a potentially edible printed chitosan‐gated transistor with a design optimized for integration in circuits. Its implementation in integrated logic gates and circuits operating at low voltage (0.7 V) is demonstrated, as well as the compatibility with an ...
Giulia Coco, Valerio Francesco Annese, Valerio Galli, Ilaria Penna, Debora Russo, Marina Veronesi, Rita Scarpelli, Stefania Sabella, Mario Caironi   +8 more
wiley   +1 more source

Externally assembled gate-all-around carbon nanotube field-effect transistor [PDF]

, 2008
In this letter, we demonstrate a gate-all-around single-wall carbon nanotube field-effect transistor. This is the first successful experimental implementation of an off-chip gate and gate-dielectric assembly with subsequent deposition on a suitable ...
Chen, Zhihong, Gordon, Roy, Farmer, Damon, Xu, Sheng, Avouris, Phaedon, Appenzeller, Joerg   +5 more
core   +1 more source

Gate-Tunable Spin Hall Effect in an All-Light-Element Heterostructure: Graphene with Copper Oxide [PDF]

, 2023
Graphene is a light material for long-distance spin transport due to its low spin–orbit coupling, which at the same time is the main drawback for exhibiting a sizable spin Hall effect. Decoration by light atoms has been predicted to enhance the spin Hall
Josep Ingla-Aynés (2880350), Nerea Ontoso, Nerea Ontoso (6203885), Luis E. Hueso, Haozhe Yang, Eoin Dolan, Maider Ormaza (1351629), Frederik Schiller (1395367), Frederik Schiller, Fèlix Casanova (2810452), C.K. Safeer (15410426), Luis E. Hueso (294043), Marco Gobbi, Haozhe Yang (1498276), Franz Herling (6203876), Zhendong Chi, Maider Ormaza, C.K. Safeer, Marco Gobbi (212235), Fèlix Casanova, Beatriz Martín-García (1856131), Josep Ingla-Aynés, Franz Herling, Beatriz Martín-García, Eoin Dolan (15410423), Zhendong Chi (10097635)   +25 more
core   +1 more source