Results 71 to 80 of about 85,724 (295)

3-Levels Vertically Stacked Si Nanosheet GAA pFETs with Low-Temperature Interface Treatment for Cryogenic Application

Nanomaterials
Cryogenic CMOS technology provides a promising approach to surpass the Boltzmann limit and advance Moore’s Law, addressing the increasing demand for high-performance computing. However, at cryogenic temperatures, the subthreshold swing (SS) of the device
Lewen Qian, Tao Liu, Meicheng Liao, Xinlong Guo, Saisheng Xu, Min Xu, David Wei Zhang   +6 more
doaj   +1 more source

Oxygen‐Tunnel Indium Tin Oxide Vertical Channel Transistors with Enhanced Current Density and Reliability for Monolithic 3D Compute‐In‐Memory Systems

Advanced Functional Materials, EarlyView.
Oxygen‐tunnel (OT) indium tin oxide (ITO) vertical channel transistors (VCTs) enable reliable, high‐density gain‐cell memory for monolithic 3D integration. A sandwiched SiN/SiO2/SiN OT stack selectively regulates oxygen transport, suppressing parasitic electrode oxidation while stabilizing channel oxygen vacancies, thereby suppressing carrier injection
Hyeonho Gu, Haksoon Jung, Yongwoo Lee, Hoichang Jeong, Yanfeng Zhao, Heesoo Yang, Minho Park, Hyeonjin Lee, Seunghun Baek, Minju Song, Junghwan Kim, Youngmin Jo, Hyunjin Park, Munhyeon Kim, Jae‐Joon Kim, Kyuho Jason Lee, Byungjo Kim, Jimin Kwon   +17 more
wiley   +1 more source

High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-kappa/Metal Gate [PDF]

, 2014
We present a vertical gate-all-around Si nanowire (SiNW) metal-oxide-semiconductor field-effect transistor with high-κ dielectric and TiN metal gate. The process flow is fully compatible with CMOS technologies.
Rao, Rajesh, Mathew, Leo, Banerjee, Sanjay K., Register, Leonard F., Ekerdt, John G., Zhai, Yujia, Palard, Marylene, Chopra, Sonali   +7 more
core   +1 more source

Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology [PDF]

, 2021
An optimization study of silicon gate-all-around (GAA) devices based on technology computer-aided design tools is presented in this paper. GAA technology guidelines and solutions are provided for low power applications in the 5 nm CMOS technology node ...
Gundu, Anil Kumar, Kursun, Volkan, Anil Kumar Gundu, Volkan Kursun   +3 more
core   +1 more source

BCB Evaluation of High-Performance and Low-Leakage Three-Independent-Gate Field-Effect Transistors

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2018
Three-independent-gate field-effect transistors (TIGFETs) are a promising next-generation device technology. Their controllable-polarity capability allows for superior design of arithmetic and sequential logic gates.
Jorge Romero-Gonzalez, Pierre-Emmanuel Gaillardon   +1 more
doaj   +1 more source

Conical surrounding gate MOSFET: a possibility in gate-all-around family

Advances in Natural Sciences: Nanoscience and Nanotechnology, 2016
In this paper a new conical surrounding gate metal-oxide-semiconductor field effect transistor (MOSFET) with triple-material gate has been proposed and verified using TCAD device simulator from Synopsis. The electrostatic performance of conical model with different tapering ratios is extensively investigated and compared with that of cylindrical model (
B Jena, B S Ramkrishna, S Dash, G P Mishra   +3 more
openaire   +1 more source

Spin Injection Of Exciton–Polaritons With Halide Perovskites At Room Temperature

Advanced Functional Materials, EarlyView.
A monolithic Tamm‐plasmon microcavity embedding a two‐dimensional halide perovskite enables room‐temperature spin injection of exciton‐polaritons under quasi‐resonant optical excitation. Polarization‐resolved spectroscopy reveals partial preservation of the injected spin in the lower polariton branch, while bare excitons remain fully depolarized.
Elena Sendarrubias Arias‐Camisón, Maksim Lednev, Jorge Cuadra, Raúl Gago, Luis Viña, Francisco José García Vidal, Johannes Feist, Ferry Prins, Carlos Antón Solanas   +8 more
wiley   +1 more source

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs [PDF]

, 2012
We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels.
De Micheli, Giovanni, S. Frache, Zhang, Jian, J. Zhang, Sacchetto, Davide, G. De Micheli, Gaillardon, Pierre-Emmanuel Julien Marc, Leblebici, Yusuf, De Marchi, Michele, D. Sacchetto, M. De Marchi, P.-E. Gaillardon, Frache, Stefano, Y. Leblebici   +13 more
core   +1 more source

Trap Identification in Gate-All-Around Vertically Stacked Si n-channel Nanosheet FETs [PDF]

, 2023
International audienceIn this article low frequency noise (LFN) spectroscopy in n-type Si-channel gate-all-around (GAA) vertically stacked lateral nanosheet (NS) FETs with different numbers of nanosheets, and gate lengths is applied. From the temperature
Tahiat, Abderrahim, Cretu, Bogdan, Veloso, Anabela, Simoen, Eddy   +3 more
core   +1 more source

Swelling‐Programmed Topographical Guidance for Dynamic Spheroid Self‐Assembly via a Mechanochemical Hydrogel Niche

Advanced Functional Materials, EarlyView.
A swelling‐programmed micropatterned hydrogel guides adherent cells through a controlled transition from cell–matrix anchoring to cadherin‐mediated cell–cell compaction, enabling rapid assembly of high‐viability spheroids with defined size and morphology.
Han Gyeol Nam, Seon Yeong Chae, Young Woo Kwon, Hye Jin Heo, Hye Rin Lee, Ji Hyeok Lee, Dong‐Wook Han, Yun Hak Kim, Suck Won Hong   +8 more
wiley   +1 more source