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SEU-hardened resistive-load static RAMs
IEEE Transactions on Nuclear Science, 1991A charge partitioning (CP) design technique for MOS resistive-load static RAMs (RMOS SRAMs) is presented. This technique, when applied to RMOS SRAMs with specific capacitance attributes, may produce significant SEU error-rate control without sacrifices in area or power consumption.
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Collusion-Resistant Functional Encryption for RAMs
2022Prabhanjan Ananth +3 more
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Investigation of DPA Resistance of Block RAMs in FPGAs
2010Security at low cost is an important factor for cryptographic hardware implementations. Unfortunately, the security of cryptographic implementations is threatened by Side Channel Analysis (SCA). SCA attempts to discover the secret key of a device by exploiting implementation characteristics and bypassing the algorithm’s mathematical security ...
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Resistive RAM-based PUF: Challenges and Opportunities
2023 IEEE 16th Dallas Circuits and Systems Conference (DCAS), 2023S M Mojahidul Ahsan +3 more
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Reaction-Drift Model for Switching Transients in Pr₀.₇Ca₀.₃MnO₃-Based Resistive RAM
IEEE Transactions on Electron Devices, 2020Vivek Saraswat +2 more
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