Results 11 to 20 of about 18,097,747 (302)
Single-Event Effects in CMOS Image Sensors [PDF]
In this paper, 3T active pixel sensors (APS) are exposed to heavy ions (N, Ar, Kr, Xe), and single-event effects (SEE) are studied. Devices were fully functional during exposure, no single-event latch-up (SEL) or single-event functional interrupt (SEFI) happened.
Lalucaa, Valerian +4 more
openaire +6 more sources
The pulsed laser has gradually become the standard method of studying the single-event effects of micro-nano devices, and it is a powerful supplement to heavy ion experiments on single-event effects.
Heng An +6 more
doaj +2 more sources
Design for mitigation of single event effects
Various fault tolerant techniques can be employed to mitigate SEUs, SETs and SELs. However, such techniques usually inquire high hardware, speed and power penalty that most commercial applications could not afford. This presentation concerns low cost mitigation techniques for single-event effects induced by alpha particles and atmospheric neutrons in ...
Nicolaidis, M., M. Nicolaidis
openaire +3 more sources
Bootstrapped Driver and the Single-Event-Upset Effect [PDF]
As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP)
Mohammed Al-daloo +3 more
openaire +3 more sources
Effect of Temperature on Single Event Latchup Sensitivity [PDF]
Single-Event Latchup (SEL) concerns CMOS technology as a major reliability issue and it is influenced by different parameters. In this work, the effect of the temperature variation on SEL has been investigated and its effect has been analyzed combining the variation of three parameters related to the geometry and to the design of the component: doping ...
S. Guagliardo +7 more
openaire +2 more sources
Simulation of Single-Event Transient Effect for GaN High-Electron-Mobility Transistor
A GaN high-electron-mobility transistor (HEMT) was simulated using the semiconductor simulation software Silvaco TCAD in this paper. By constructing a two-dimensional structure of GaN HEMT, combined with key models such as carrier mobility, the effects ...
Zhiheng Wang +11 more
doaj +1 more source
Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node
Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should
Christopher J. Elash +6 more
doaj +1 more source
Single-Event Upset Analysis and Protection in High Speed Circuits [PDF]
The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at
Lofti-Kamran, P. +13 more
core +1 more source
NAIRAS Model Run‐On‐Request Service at CCMC
The Nowcast of Aerospace Ionizing RAdiation System (NAIRAS) version 3 model is available to the community through the Community Coordinated Modeling Center run‐on‐request (RoR) service.
C. J. Mertens +8 more
doaj +1 more source
Custom Scrubbing for Robust Configuration Hardening in Xilinx FPGAs
The usage of SRAM-based Field Programmable Gate Arrays on High Energy Physics detectors is mostly limited by the sensitivity of these devices to radiation-induced upsets in their configuration.
Raffaele Giordano +3 more
doaj +1 more source

