Results 11 to 20 of about 13,092 (260)
Single event upset reinforcement technology of DICE flip-flop based on layout design
Xibei Gongye Daxue Xuebao, 2022 D flip-flop is the basis of timing logic circuit, and SEMU phenomenon tends to be serious with the integrated circuit process size shrinking to nanometer scale.
LAI Xiaoling +4 more
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Double Node Upset Immune RHBD-14T SRAM Cell for Space and Satellite Applications
IEEE Access, 2023 Deep sub-micron memory devices play a crucial role in space electronic applications due to their susceptibility to single-event upset and double-node upset types of soft errors. When a charged particle from space hit a scaled memory circuit, the critical
Pavan Kumar Mukku, Rohit Lorenzo
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Open Astronomy, 2023 The single event effect caused by space heavy ion radiation is one of the important factors affecting the safety and operation of spacecraft on orbit.
Zhang Binquan +10 more
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A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications
Micromachines, 2023 The static random-access memory (SRAM) cells used in the high radiation environment of aerospace have become highly vulnerable to single-event effects (SEE).
Ruxue Yao +6 more
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Bootstrapped Driver and the Single-Event-Upset Effect [PDF]
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020 As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP)
Mohammed Al-Daloo +3 more
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IEEE Access, 2022 This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel.
Antonio Calomarde +3 more
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Single Event Upset: An Embedded Tutorial [PDF]
21st International Conference on VLSI Design (VLSID 2008), 2008 With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends such as transistor down-sizing, use of new materials, and system on chip architectures continue to increase the sensitivity of systems to soft errors.
Fan Wang, Vishwani D. Agrawal
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Yuanzineng kexue jishu, 2022 Single event upset (SEU) has always been an important factor affecting the reliability of spacecraft electronic equipment, which can cause anomalies in electronic equipment in orbit, and can result in serious spacecraft failure. In order to master signal
ZHAO Zhendong;TAO Wenze;LI Yancun;CHENG Yi;ZHANG Qingxiang;AN Heng;QUAN Xiaoping;ZHANG Chenguang
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Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications
Journal of Low Power Electronics and Applications, 2019 Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation.
Satheesh Kumar S, Kumaravel S
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Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch
IEEE Access, 2023 This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost profile.
Seyedehsomayeh Hatefinasab +4 more
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