Results 221 to 230 of about 13,092 (260)

Geometric Considerations in Single Event Upset Estimation

IEEE Transactions on Nuclear Science, 1985
We investigate the importance of several orientation dependent factors in estimating single event upsets due to cosmic rays. These factors include Earth's shadow, shielding and geomagnetic cutoff anisotropy, and angular dependence of device sensitivity.
John R. Letaw, Rein Silberberg, C. H. Tsao, James H. Adams   +3 more
openaire   +1 more source

A single event upset tolerant latch design

Microelectronics Reliability, 2018
Abstract This paper presents a single-event-upset tolerant latch design based on a redundant structure featuring four storage nodes (i.e. Quatro). The reference structure manifests single node upset issues when either of the two internal nodes is hit and observes a positive transient afterwards.
Haibin Wang, Xixi Dai, Yangsheng Wang, Issam Nofal, Li Cai, Zicai Shen, Wanxiu Sun, Jinshun Bi, Bo Li, Gang Guo, Li Chen, Sang Baeg   +11 more
openaire   +1 more source

Single-event upset in the PowerPC750 microprocessor

IEEE Transactions on Nuclear Science, 2001
Proton and heavy ion upset susceptibility has been measured individually for six types of storage elements in an advanced commercial processor, the PowerPC750, from two manufacturers: Motorola and IBM. Data on interfering program malfunctions was also collected. Compared to earlier PPC603e results, the upset susceptibility has decreased somewhat.
G.M. Swift, F.F. Fannanesh, S.M. Guertin, F. Irom, D.G. Millward   +4 more
openaire   +1 more source

Single Event Upset in SOS Integrated Circuits

IEEE Transactions on Nuclear Science, 1987
Single event upset (SEU) by argon and krypton ions has been observed in 1.25 micron CMOS-SOS integrated circuits. Mixed-mode PISCES-SPICE, circuit-device simulations were conducted and the calculated LET threshold compared favorably to experimental data.
J. G. Rollins, J. Choma, W. A. Kolasinski   +2 more
openaire   +1 more source

Single event upset at ground level

IEEE Transactions on Nuclear Science, 1996
Ground level upsets have been observed in computer systems containing large amounts of random access memory (RAM). Atmospheric neutrons are most likely the major cause of the upsets based on measured data using the Weapons Neutron Research (WNR) neutron beam.
openaire   +1 more source

Nuclear microprobe imaging of single-event upsets

IEEE Transactions on Nuclear Science, 1992
An imaging technique has been developed which produces micron-resolution maps of where single-event upsets occur during ion irradiation of integrated circuits. From these 'upset images' the identity and size of a circuit's upset-prone components can be directly determined.
K.M. Horn, B.L. Doyle, F.W. Sexton
openaire   +1 more source

On single event upset error manifestation

1994
This paper addresses the problem of how faults in a radiation environment primarily manifest as errors in a complex device. Previous work in the area has focused on modelling the latching of transients. In this paper this modelling task is extended to the phenomenon of double soft errors. The first error manifestation of a single event upset (SEU) in a
openaire   +1 more source

Single event upset immune GaAs memories

Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991, 1991
The author describes the design and development status of two different memory architectures which both promise immunity to upset from cosmic rays and energetic protons. The first memory is a conventional static RAM with capacitors added in the memory cell to increase the critical charge for upset above the charge deposited by natural events.
openaire   +1 more source

Detecting Single Event Upsets in Embedded Software

2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC), 2018
The past decade has seen explosive growth in the use of small satellites. Within this domain, there has been a growing trend to place more responsibility on the flight software (versus hardware) and an increasing adoption of consumer-grade microprocessors to satisfy this desire for increased processing capability while still minimizing size, weight ...
Robert Pettit, Aedan Pettit
openaire   +1 more source

Single Event Upset Hardening of Interconnects

2016
With advances in technology scaling, circuits are increasingly more sensitive to transients caused by Single Event particles. Hardening techniques for CMOS combinational logic have been developed to address the problems associated with Single Event Transients , but in these designs, SET coupling effects have been ignored.
openaire   +1 more source