Results 271 to 280 of about 214,395 (302)

Analysis of single-event transients in analog circuits

IEEE Transactions on Nuclear Science, 2000
A new methodology for understanding single-event transient (SET) phenomena in analog circuits is described. Device and circuit simulation techniques are coupled in order to reproduce experimental data obtained from the National Semiconductor LM124 operational amplifier and to determine the most sensitive parts of the integrated circuit.
P. Adell, R.D. Schrimpf, H.J. Barnaby, R. Marec, C. Chatry, P. Calvel, C. Barillot, O. Mion   +7 more
openaire   +1 more source

Single Event Transients in Digital CMOS—A Review

IEEE Transactions on Nuclear Science, 2013
The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore's Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of ...
V. Ferlet-Cavrois, L. W. Massengill, P. Gouker   +2 more
openaire   +1 more source

Single Event Transients in SiGe HBT

2017
When the high-energy charged particles strike the transistors or circuits, an amount of high-density electron hole pairs are generated, and then single event effects are produced when the electron hole pairs are collected by device terminals.
openaire   +1 more source

An analytical approach for estimation of single event transients

2016 International Conference on Emerging Technological Trends (ICETT), 2016
Transient faults are a matter of increasing concern as advanced technologies scales to smaller and smaller feature technologies. Transient errors are random faults of the hardware, which also called as soft errors. Single Event Transients (SETs) are major part of the error events which will continue to grow in the next technology nodes and affect the ...
Surya Suseelan, Pooja S Mohan
openaire   +1 more source

CMOS VLSI single event transient characterization

IEEE Transactions on Nuclear Science, 1989
The MOSIS VLSI IC process has been characterized for picosecond single-event transients for large-area diode test structures. Three test structures were designed for a CMOS, p-well, 3- mu m process, including two MOS diodes for SEU transient measurements. Devices were irradiated with 5-MeV boron ions and 5-MeV alpha -particles.
S.J. Heileman, W.R. Eisenstadt, R.M. Fox, R.S. Wagner, N. Bordes, J.M. Bradley   +5 more
openaire   +1 more source

Characterization of Single Event Transient Effects in Standard Delay Cells

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020
Standard delay cells (SDCs) are commonly used for timing synchronization in digital designs. Due to skewed transistor sizing, the SETs induced in SDCs may be stretched during propagation through the cell, thus increasing the soft error rate. In this work, the simulation analysis of Single Event Transient (SET) effects in 130 nm SDCs is presented.
Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Milos Krstic, Rolf Kraemer   +4 more
openaire   +1 more source

Probabilistic Evaluation of Analog Single Event Transients

IEEE Transactions on Nuclear Science, 2007
We propose a procedure to estimate the consequences of an analog single event transient (ASET). The method qualifies ASETs based on their frequency domain signatures and determines the probability of a single event transient induced error.
Amy V. Kauppila, Gregg L. Vaughn, Jeffrey S. Kauppila, Lloyd W. Massengill   +3 more
openaire   +1 more source

Impact of gate shapes on single event transients

2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014
3D-TCAD simulations in a 0.18um process are used to show the effect of gate shapes on the single event transients of both PMOS and NMOS. The results turn out that the SET pulse widths of enclosed layout transistors are much smaller than the standard layout transistors.
null Zhao Xinyuan, null Wang liang, null Yue Suge   +2 more
openaire   +1 more source

Single event transients in deep submicron CMOS

42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356), 2003
Single event transients (SET) occur when an energetic subatomic particle strikes a combinational logic element. The charge deposited by the particle causes a transient voltage disturbance, which can propagate to a storage element and be latched, resulting in single event upset (SEU).
K.J. Hass, J.W. Ambles
openaire   +1 more source

Single Event Transient Suppressor for Flip-Flops

IEEE Transactions on Nuclear Science, 2010
Some single event upset (SEU)-hardened flip-flops cannot mitigate single event transients (SET) that come from the upstream combinational circuits and propagate to the data inputs of flip-flops near the capturing clock edge. This paper presents a SET suppressor that can mitigate such SETs.
Xiaoxuan She, N. Li, R. Mariad Carlson, D. Oliswy Erstad   +3 more
openaire   +1 more source