Results 11 to 20 of about 312,625 (306)

Single event upset reinforcement technology of DICE flip-flop based on layout design

Xibei Gongye Daxue Xuebao, 2022
D flip-flop is the basis of timing logic circuit, and SEMU phenomenon tends to be serious with the integrated circuit process size shrinking to nanometer scale.
LAI Xiaoling, ZHANG Jian, JU Ting, ZHU Qi, GUO Yangming   +4 more
doaj   +1 more source

Double Node Upset Immune RHBD-14T SRAM Cell for Space and Satellite Applications

IEEE Access, 2023
Deep sub-micron memory devices play a crucial role in space electronic applications due to their susceptibility to single-event upset and double-node upset types of soft errors. When a charged particle from space hit a scaled memory circuit, the critical
Pavan Kumar Mukku, Rohit Lorenzo
doaj   +1 more source

Single-Event Upset Analysis and Protection in High Speed Circuits [PDF]

, 2006
The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at
Benso, Alfredo, Di Carlo, Stefano, Di Natale, Giorgio, Hosseinabady, M., Lofti-Kamran, P., Prinetto, Paolo Ernesto   +5 more
core   +1 more source

Monitor of the single event upsets and linear energy transfer of space radiation on the Beidou navigation satellites

Open Astronomy, 2023
The single event effect caused by space heavy ion radiation is one of the important factors affecting the safety and operation of spacecraft on orbit.
Zhang Binquan, Zhang Shenyi, Shen Guohong, Tuo Changsheng, Zhang Xin, Zhang Huanxin, Quan Lin, Tian Chao, Hou Donghui, Zhou Ping, Ji Wentao   +10 more
doaj   +1 more source

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications

Micromachines, 2023
The static random-access memory (SRAM) cells used in the high radiation environment of aerospace have become highly vulnerable to single-event effects (SEE).
Ruxue Yao, Hongliang Lv, Yuming Zhang, Xu Chen, Yutao Zhang, Xingming Liu, Geng Bai   +6 more
doaj   +1 more source

Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs [PDF]

, 2015
Dual- and triple-well bulk CMOS SRAMs fabricated at the 28-nm node were tested using alpha particles and heavy-ions over a range of supply voltages.
Bartz, Brandon, Bhuva, Bharat L., Chatterjee, Indranil, Gupta, Saket, Monzel, Carl, Narasimham, Balaji, Reed, Robert A., Schrimpf, Ronald D., Vedula, Narayana, Wang, Jung K.   +9 more
core   +2 more sources

Bootstrapped Driver and the Single-Event-Upset Effect [PDF]

IEEE Transactions on Circuits and Systems I: Regular Papers, 2020
As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP)
Mohammed Al-Daloo, Mohamed A. Abufalgha, Alex Yakovlev, Basel Halak   +3 more
openaire   +3 more sources

Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact

IEEE Access, 2022
This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel.
Antonio Calomarde, Salvador Manich, Antonio Rubio, Francisco Gamiz   +3 more
doaj   +1 more source

Design and Test of Principle Prototype of Space Single Event Upset Discriminating and Positioning System

Yuanzineng kexue jishu, 2022
Single event upset (SEU) has always been an important factor affecting the reliability of spacecraft electronic equipment, which can cause anomalies in electronic equipment in orbit, and can result in serious spacecraft failure. In order to master signal
ZHAO Zhendong;TAO Wenze;LI Yancun;CHENG Yi;ZHANG Qingxiang;AN Heng;QUAN Xiaoping;ZHANG Chenguang
doaj  

Single Event Upset: An Embedded Tutorial [PDF]

21st International Conference on VLSI Design (VLSID 2008), 2008
With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends such as transistor down-sizing, use of new materials, and system on chip architectures continue to increase the sensitivity of systems to soft errors.
Fan Wang, Vishwani D. Agrawal
openaire   +1 more source