Results 21 to 30 of about 312,625 (306)

Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset

IEEE Journal of the Electron Devices Society, 2020
This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel field effect transistor (DG TFET). The mitigation technique for the data recovery after the heavy ion strike is discussed.
M. Pown, B. Lakshmi
doaj   +1 more source

Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

IEEE Access, 2023
This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost profile.
Seyedehsomayeh Hatefinasab, Alfredo Medina-Garcia, Diego P. Morales, Encarnacion Castillo, Noel Rodriguez   +4 more
doaj   +1 more source

Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications

Journal of Low Power Electronics and Applications, 2019
Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation.
Satheesh Kumar S, Kumaravel S
doaj   +1 more source

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

IEEE Access, 2022
As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in ...
Seyedehsomayeh Hatefinasab, Akiko Ohata, Alfonso Salinas, Encarnacion Castillo, Noel Rodriguez   +4 more
doaj   +1 more source

Low-Power Radiation-Hardened Static Random Access Memory with Enhanced Read Stability for Space Applications

Applied Sciences
In space environments, radiation particles affect the stored values of SRAM cells, and these effects, such as single-event upsets (SEUs) and single-event multiple-node upsets (SEMNUs), pose a threat to the reliability of systems used in the space ...
Hong-Geun Park, Sung-Hun Jo
doaj   +1 more source

First evaluation of neutron induced single event effects on the CMS barrel muon electronics [PDF]

, 2000
Neutron irradiation tests of the currently available electronics for the CMS barrel muon detector were performed using Thermal and fast neutrons at E< 11MeV.
Agosteo, S, Castellani, L, D'Angelo, G, Favalli, A, Lippi, I, Martinelli, R, Zotto, P L   +6 more
core   +1 more source

Single-event upset simulation and detection in configuration memory

Frontiers in Space Technologies
Single-event upsets (SEUs) from radiation strikes in configuration memory are potentially catastrophic due to their widespread effects. For field-programmable gate arrays (FPGAs), faults in configuration memory propagate into the implemented logic design
Hezekiah Austin, Chris Major, Chris Major, Colter Barney, Justin Williams, Zachary Becker, Mackenzie Smith, Brock LaMeres, Brock LaMeres   +8 more
doaj   +1 more source

Active Radiation-Hardening Strategy in Bulk FinFETs

IEEE Access, 2020
In this article, we present a new method to mitigate the effect of the charge collected by trigate FinFET devices after an ionizing particle impact. The method is based on the creation of an internal structure that generates an electrical field that ...
Antonio Calomarde, Antonio Rubio, Francesc Moll, Francisco Gamiz   +3 more
doaj   +1 more source

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

IEEE Access, 2019
This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs).
Aibin Yan, Jun Zhou, Yuanjie Hu, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen   +6 more
doaj   +1 more source

Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node

Applied Sciences, 2022
Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should
Christopher J. Elash, Zongru Li, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang, Shuting Shi   +6 more
doaj   +1 more source