Results 141 to 150 of about 253 (176)

Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2018
This paper analyzes the effects of single event upsets (SEUs) on the user memory of a Viterbi decoder implemented on an SRAM based FPGA. First, an FPGA Viterbi decoder implementation is used to study the structures that are mapped to user memory. Then, the SEUs tolerance capability for each of those structures is analyzed theoretically.
Zhen Gao, Lina Yan, Jinhua Zhu, Ruishi Han, Pedro Reviriego   +4 more
openaire   +1 more source

Experimental Evidence for a New Single-Event Upset (SEU) Mode in a CMOS SRAM Obtained from Model Verification

IEEE Transactions on Nuclear Science, 1987
Modeling of SEU has been done in a CMOS static RAM containing one-micron channel-length transistors fabricated from a P-well epilayer process using both circuit-and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator ...
J. A. Zoutendyk, L. S. Smith, G. A. Soli, R. Y. Lo   +3 more
openaire   +1 more source

System-Level Modeling and Analysis of the Vulnerability of a Processor to Single-Event Upsets (SEUs)

2019
In this chapter, an efficient system-level approach to model and analyze the propagation of SEUs in a simple processor is introduced. The high-level model of the processor is formalized as a Continuous-Time Markov Chain (CTMC). Probabilistic model checking (PMC) is utilized to exhaustively estimate the impact of SEUs on the behavior of the processor ...
Marwan Ammar, Ghaith Bany Hamad, Otmane Ait Mohamed, Yvon Savaria   +3 more
openaire   +2 more sources

Total-dose and single-event-upset (SEU) resistance in advanced SRAMs fabricated on SOI using 0.2 μm design rules

2001 IEEE Radiation Effects Data Workshop. NSREC 2001. Workshop Record. Held in conjunction with IEEE Nuclear and Space Radiation Effects Conference (Cat. No.01TH8588), 2002
We measured total-dose and single-event-upset (SEU) resistance in advanced 128-Kbit SRAMs fabricated on SOI using 0.2 /spl mu/m design rules. Our results indicate that the 128-Kbit SRAMs can be used in specific space technologies.
K. Hirose, H. Saito, M. Akiyama, M. Arakaki, Y. Kuroda, S. Ishii, K. Nakano   +6 more
openaire   +1 more source

Single event upset (SEU): Diagnostic and error correction system for avioncs device

2009
In aerospace applications, Commercial-Off-The-Shelf (COTS) Field programmable Gate Array (FPGA) is becoming increasingly attractive by offering low-cost solutions, simplicity and flexibility. This research faces the problem of disturbance induced by high energy particles on electronic devices.
CIANI, LORENZO, CATELANI, MARCANTONIO, L. Veltroni   +2 more
openaire   +1 more source

Single Event Latchup (SEL) and Single Event Upset (SEU) Evaluation of Xilinx 7nm Versal™ ACAP programmable logic (PL)

2021 IEEE Nuclear and Space Radiation Effects Conference (NSREC), 2021
Pierre Maillard, Yanran P. Chen, Jeff Barton, Martin L. Voogel   +3 more
openaire   +1 more source

Efficient protection of polar decoders against Single Event Upsets (SEUs) on user memories

Microelectronics Reliability, 2023
Dong Tian, Zhen Gao, Ruize Wang, Qiang Liu, Anees Ullah, Pedro Reviriego   +5 more
openaire   +1 more source

Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2022
Semiu A. Olowogemo, Hao Qiu, Bor-Tyng Lin, William H. Robinson, Daniel B. Limbrick   +4 more
openaire   +1 more source

Diagnostic and error correction system for avionics devices in presence of single event upset (SEU)

2013
In aerospace applications, Commercial-Off-The-Shelf (COTS) Field programmable Gate Array (FPGA) is becoming increasingly attractive by offering low-cost solutions, simplicity and flexibility. This research faces the problem of disturbance induced by high energy particles on electronic devices.
CATELANI, MARCANTONIO, CIANI, LORENZO
openaire   +1 more source

Single-Event-Upset (SEU) Mitigation Techniques for Routing Resources of SRAM-FPGA

International Journal of Advancements in Computing Technology, 2012
Cheng Gao -, Wei Guo -, Jiaoying Huang -
openaire   +1 more source