Results 11 to 20 of about 41,687 (303)

Monitor of the single event upsets and linear energy transfer of space radiation on the Beidou navigation satellites

Open Astronomy, 2023
The single event effect caused by space heavy ion radiation is one of the important factors affecting the safety and operation of spacecraft on orbit.
Zhang Binquan, Zhang Shenyi, Shen Guohong, Tuo Changsheng, Zhang Xin, Zhang Huanxin, Quan Lin, Tian Chao, Hou Donghui, Zhou Ping, Ji Wentao   +10 more
doaj   +1 more source

Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node

Applied Sciences, 2022
Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should
Christopher J. Elash, Zongru Li, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang, Shuting Shi   +6 more
doaj   +1 more source

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

IEEE Access, 2019
This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs).
Aibin Yan, Jun Zhou, Yuanjie Hu, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen   +6 more
doaj   +1 more source

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

IEEE Access, 2022
As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in ...
Seyedehsomayeh Hatefinasab, Akiko Ohata, Alfonso Salinas, Encarnacion Castillo, Noel Rodriguez   +4 more
doaj   +1 more source

Custom Scrubbing for Robust Configuration Hardening in Xilinx FPGAs

Instruments, 2019
The usage of SRAM-based Field Programmable Gate Arrays on High Energy Physics detectors is mostly limited by the sensitivity of these devices to radiation-induced upsets in their configuration.
Raffaele Giordano, Dario Barbieri, Sabrina Perrella, Roberto Catalano   +3 more
doaj   +1 more source

Bootstrapped Driver and the Single-Event-Upset Effect [PDF]

IEEE Transactions on Circuits and Systems I: Regular Papers, 2020
As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP)
Mohammed Al-Daloo, Mohamed A. Abufalgha, Alex Yakovlev, Basel Halak   +3 more
openaire   +3 more sources

Formal Verification of Fault-Tolerant Hardware Designs

IEEE Access, 2023
Digital circuits for space applications can suffer from operation failures due to radiation effects. Error detection and mitigation techniques are widely accepted solutions to improve dependability of digital circuits under Single Event Upsets (SEUs) and
Luis Entrena, Antonio J. Sanchez-Clemente, Luis A. Garcia-Astudillo, Marta Portela-Garcia, Mario Garcia-Valderas, Almudena Lindoso, Roberto Sarmiento   +6 more
doaj   +1 more source

Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs [PDF]

, 2016
This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the
Ayoubi, Rafic, Clemente Barreira, Juan Antonio, El Falou, Wassim, Mansour, Wassim, Mecha López, Hortensia, Serrano, Felipe, Velazco, Raoul, Ziade, Haissam   +7 more
core   +4 more sources

Single Event Upset: An Embedded Tutorial [PDF]

21st International Conference on VLSI Design (VLSID 2008), 2008
With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends such as transistor down-sizing, use of new materials, and system on chip architectures continue to increase the sensitivity of systems to soft errors.
Fan Wang, Vishwani D. Agrawal
openaire   +1 more source

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

IEEE Access, 2019
Transient errors induced by radiations cause bit-flips in flip-flops (flip-flop soft errors). Modeling the error resilience level of a target system for flip-flop soft errors is a crucial step to achieve a cost-effective error resilience solution.
Hyungmin Cho, Kon-Woo Kwon
doaj   +1 more source