Results 11 to 20 of about 7,396,207 (304)
Mitigating bit flips or single event upsets in epilepsy neurostimulators [PDF]
Objectives: The objective of this study was to review software errors known as single event upsets (SEUs) or bit flips due to cosmic rays in epilepsy neurostimulators. Materials and methods: A case report of a single event upset or bit flip is discussed;
Alice X. Dong +4 more
doaj +3 more sources
This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs).
Aibin Yan +6 more
doaj +2 more sources
Soft-Error-Resilient Static Random Access Memory with Enhanced Write Ability for Radiation Environments [PDF]
As semiconductor technologies advance, SRAM cells deployed in space systems face heightened sensitivity to radiation-induced soft errors. In conventional 6T SRAM, when high-energy particles strike sensitive nodes, single-event upsets (SEUs) may occur ...
Se-Yeon Park, Eun Gyo Jeong, Sung-Hun Jo
doaj +2 more sources
Low power and high-speed quadrate node upset tolerant latch design using CNTFET [PDF]
Scalability, leakage, short-channel effects, and reliability problems are some of the difficulties facing the semiconductor industry as it continues to experience a reduction in size.
Shaik Asiya, Satheesh Kumar S
doaj +2 more sources
Single Event Upsets in the ATLAS IBL Frontend ASICs
During operation at instantaneous luminosities of up to 2 10^34/cm^2/s the frontend chips of the ATLAS innermost pixel layer (IBL) experienced single event upsets affecting its global registers as well as the settings for the individual pixels, causing ...
Takubo, Yosuke
core +3 more sources
Single-Event Upset Analysis and Protection in High Speed Circuits [PDF]
The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at
Lofti-Kamran, P. +13 more
core +1 more source
Custom Scrubbing for Robust Configuration Hardening in Xilinx FPGAs
The usage of SRAM-based Field Programmable Gate Arrays on High Energy Physics detectors is mostly limited by the sensitivity of these devices to radiation-induced upsets in their configuration.
Raffaele Giordano +3 more
doaj +1 more source
Highly Reliable Quadruple-Node Upset-Tolerant D-Latch
As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in ...
Seyedehsomayeh Hatefinasab +4 more
doaj +1 more source
Measurements of Single Event Upset in ATLAS IBL
Published by Inst.
Balbi, G. +27 more
openaire +7 more sources
Observations of Single-Event Memory Upsets On the UoSAT-2 Satellite [PDF]
This paper describes observations of single-event memory upsets in the UoSAT-2 satellite Digital Communications Experiment. Two years of SEU observations for Harris 6564 memories are included, presented both as error rate statistics and as a map of ...
Ward, Jeff
core +1 more source

