Results 21 to 30 of about 41,687 (303)
IEEE Access, 2022 SRAM cells are widely used to design memory blocks of, e.g., caches, register files, and translation lookaside buffers. Depending on the SRAM application, the design requirements are different.
Azam Seyedi +2 more
doaj +1 more source
Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons [PDF]
, 2015 This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data.
Agapito Serrano, Juan Andrés +8 more
core +6 more sources
Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications
IEEE Access, 2023 With technology scaling, transistor sizing as well as the distance between them, is decreasing rapidly, thereby reducing the critical charge of sensitive nodes. This reduction makes SRAM cells used for aerospace applications more susceptible to radiation
Soumitra Pal +3 more
doaj +1 more source
Design of Static Random-Access Memory Cell for Fault Tolerant Digital System
Applied Sciences, 2022 This paper comparatively analyzes the static random-access memory (SRAM) cell designs for fault tolerance. Since SRAM cells are sensitive to radiation-induced single event upsets, various circuit-level approaches have been applied.
Taehwan Yoon, Jihwan Park, Hanwool Jeong
doaj +1 more source
Radiation-Hardened 20T SRAM with Read and Write Optimization for Space Applications
Applied SciencesWith continued CMOS scaling, transistor miniaturization has significantly raised SRAM integration density while lowering the critical charge (Qc), increasing cell vulnerability to spaceborne high-energy particles.
Kon-Woo Kim, Eun Gyo Jeong, Sung-Hun Jo
doaj +1 more source
Assessing Scrubbing Techniques for Xilinx SRAM-based FPGAs in Space Applications [PDF]
, 2014 SRAM-based FPGAs are becoming increasingly attractive for use in space applications due to their reconfigurability and signal processing capabilities, as well as their increasing speed and capacity.
Brosser, Fredrik +3 more
core +1 more source
IEEE AccessDesigning fault resilient storage components is a significant challenge in radiation-hardened systems, as CMOS scaling causes systems to be more susceptible to radiation-induced Multiple-Node Upsets (MNUs). The proposed Triple input-Dual output C-element-
Shaik Asiya, Rajeev Pankaj Nelapati
doaj +1 more source
Bias Dependence of Single-Event Upsets in 16 nm FinFET D-Flip-Flops [PDF]
, 2015 With fabrication processes migrating from planar devices to FinFETs, the differences in physical structure necessitate evaluating the SEU mechanisms of FinFET-based circuits. Since FinFET-based bi-stable circuits have shown better stability at low supply
Anvar, Ali +11 more
core +2 more sources
Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications
Journal of Low Power Electronics and Applications, 2019 Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation.
Satheesh Kumar S, Kumaravel S
doaj +1 more source
SAMPEX Measurements of Heavy Ions Trapped in the Magnetosphere [PDF]
, 1993 New observations of >15 MeV/nuc trapped heavy ions with Z 2 2 have been made by the SAMPEX spacecraft in low polar orbit. The composition of these ions, which are located primarily around L = 2, is dominated by He, N, O, and Ne. The N, O, and Ne ions
Blake, J. B. +6 more
core +1 more source