Results 51 to 60 of about 101 (95)

Mitigating Soft Errors in System-on-Chip Design

2008 The 9th International Conference for Young Computer Scientists, 2008
With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation scaling. Technology trends such as transistor downsizing, use of new materials and high performance computer architecture continue to increase the sensitivity of systems to soft errors.
Hai Yu, Fan Xiaoya
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Circuit Level Design Methods to Mitigate Soft Errors

2020 IEEE Latin-American Test Symposium (LATS), 2020
The mitigation of soft errors should be considered in all design abstraction levels, from a high level to the physical one. This tutorial is focused on the circuit and physical design levels. Transistor reordering or transistor arrangements is an important way to improve robustness.
Ricardo A. L. Reis, Cristina Meinhardt, Alexandra L. Zimpeck, Leonardo Heitich Brendler, Leonardo B. Moraes   +4 more
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A New Mitigation Approach for Soft Errors in Embedded Processors

IEEE Transactions on Nuclear Science, 2007
Embedded processors, like for example processor macros inside modern FPGAs, are becoming widely used in many applications. As soon as these devices are deployed in radioactive environments, designers need hardening solutions to mitigate radiation-induced errors.
ABATE, FRANCESCO, STERPONE, Luca, VIOLANTE, MASSIMO   +2 more
openaire   +3 more sources

Using value similarity of registers for soft error mitigation

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015
Soft errors caused by the cosmic particles or the radiation from the packaging material of the integrated circuits are an increasingly important design problem. With the shrinking feature sizes, the datapath components of the out-of-order superscalar pipeline are becoming more prone to soft errors. Being the major data holding component in contemporary
Abdulaziz Eker, Oguz Ergin
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Soft Error Mitigation in Soft-Core Processors

2016
This chapter aims to present different approaches and techniques available in literature regarding the fault mitigation on soft-core processors, with an especial emphasis on those ones involving hardware/software hybrid-based solutions.
Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Felipe Restrepo-Calle   +2 more
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Soft error vulnerability aware process variation mitigation

2009 IEEE 15th International Symposium on High Performance Computer Architecture, 2009
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior studies have shown that chip operating frequency and leakage power can have large variations due to fluctuations in transistor gate length and sub-threshold voltage. In this work,
Xin Fu 0001, Tao Li 0006, José A. B. Fortes   +2 more
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Compiler-Directed Soft Error Mitigation for Embedded Systems

IEEE Transactions on Dependable and Secure Computing, 2012
The protection of processor-based systems to mitigate the harmful effect of transient faults (soft errors) is gaining importance as technology shrinks. At the same time, for large segments of embedded markets, parameters like cost and performance continue to be as important as reliability.
Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Felipe Restrepo-Calle, Francisco R. Palomo, Hipólito Guzmán-Miranda, Miguel A. Aguirre   +5 more
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Software-Level Soft-Error Mitigation Techniques

2010
Several application domains exist, where the effects of Soft Errors on processor-based systems cannot be faced by acting on the hardware (either by changing the technology, or the components, or the architecture, or whatever else). In these cases, an attractive solution lies in just modifying the software: the ability to detect and possibly correct ...
REBAUDENGO, Maurizio, SONZA REORDA, Matteo, VIOLANTE, MASSIMO   +2 more
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A method for issue queue soft error vulnerability mitigation

2016 17th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD), 2016
Issue queue is a critical structure in the pipeline and more vulnerable to soft-error strikes. Reducing soft error vulnerability of issue queue cannot be ignored in microprocessor reliability design. Instructions clog in issue queue caused by instruction flow mix and functional unit configuration mismatch.
Liu Tang, Zhangqin Huang
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Design techniques for soft-error mitigation

2010 IEEE International Conference on Integrated Circuit Design and Technology, 2010
In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft-errors, a concern in the past for space applications, became a reliability issue at ground-level. Alpha particles and atmospheric neutrons induce single event upsets (SEU) affecting memory cells, latches and flip-flops, and single event transients ...
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