Results 71 to 80 of about 101 (95)

Soft Error Mitigation on Dual Rail Latch

Applied Mechanics and Materials, 2016
A single event upset (SEU) or soft error is defined as a temporary error on digital electronics due to the effect of radiation. Such an error can cause system failure, e.g. a deadlock in an asynchronous system or production of incorrect outputs due to data corruption.
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Temporal redundancy latch-based architecture for soft error mitigation

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017
Current transients caused by energetic particle strikes are a serious threat for digital circuits in aerospace applications. Such single-event transients (SETs) can corrupt the circuit state, with possibly devastating consequences. Although it is possible to protect circuits with spatial redundancy techniques, the area and power overhead is high ...
Robert Schmidt 0003, Alberto García Ortiz, Görschwin Fey   +2 more
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Soft-error mitigation by means of decoupled transactional memory threads

Distributed Computing, 2014
CMOS scaling exacerbates hardware errors making reliability a big concern for recent and future microarchitecture designs. Mechanisms to provide fault tolerance in architectures must accomplish several objectives such as low performance degradation, power consumption and area overhead.
Daniel Sánchez 0004, Juan M. Cebrian, José M. García 0001, Juan L. Aragón   +3 more
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Soft error rate estimation and mitigation for SRAM-based FPGAs

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, 2005
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Previous techniques on FPGA SER estimation are based on time-consuming fault injection and simulation
Ghazanfar Asadi, Mehdi Baradaran Tahoori
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Optimal soft error mitigation in wireless communication using approximate logic circuits

Sustainable Computing: Informatics and Systems, 2021
Gautam Srivastava, Joseph Henry Anajemba, James Adu Ansere   +2 more
exaly  

Static analysis to mitigate soft errors in register files

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009
Jongeun Lee, Aviral Shrivastava
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SOFIA: An automated framework for early soft error assessment, identification, and mitigation

Journal of Systems Architecture, 2022
Ricardo Reis, Jonas Gava, Vitor Bandeira   +2 more
exaly  

RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique

IFIP Advances in Information and Communication Technology, 2021
Ricardo Reis, Jonas Gava, Luciano Ost
exaly  

Soft error mitigation in asynchronous networks on chip.

2012
In advanced deep submicron technologies, the aggressive scaling of the clock to increasingly higher frequencies has now terminated. At the circuit top level, global clocking is not feasible anymore, which has led to the popularization of the Globally Asynchronous Locally Synchronous paradigm for constructing complex system on chip devices, with local ...
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Reliability analysis of ensemble fault tolerance for soft error mitigation against complex radiation effect

Reliability Engineering and System Safety, 2022
Chong Bian, Shunkun Yang, Qi Shao
exaly