A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method. [PDF]
We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements ...
Alshahry SM +3 more
europepmc +3 more sources
A 96-Channel FPGA-based Time-to-Digital Converter [PDF]
We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) in the CDF Experiment at the Fermilab Tevatron.
Affolder +16 more
core +4 more sources
A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification [PDF]
This paper investigates a novel cyclic time-to-digital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop).
M. Rezvanyvardom, E. Farshidi
doaj +4 more sources
Firmware-only implementation of time-to-digital converter (TDC) in field-programmable gate array (FPGA) [PDF]
A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array, (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter.
Jinyuan Wu, Zonghan Shi, Irena Wang
semanticscholar +2 more sources
PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks [PDF]
Recently, cyberattacks on Controller Area Network (CAN) which is one of the automotive networks are becoming a severe problem. CAN is a protocol for communicating among Electronic Control Units (ECUs) and it is a de-facto standard of automotive networks.
Shuji Ohira +3 more
semanticscholar +2 more sources
62.5 ps LSB resolution multiphase clock Time to Digital Converter (TDC) implemented on FPGA
A 13-bit Time to Digital Converter is implemented using multiphase clock technique. Xilinx’s Virtex 5 FPGA platform is used to realize the TDC architecture.
Mahantesh Mattada, Hansraj Guhilot
doaj +2 more sources
This paper describes a time-to-digital converter (TDC) with ~1.2 ps resolution and ~327 mus dynamic range suitable for laser range-finding application for example. The resolution of ~1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive ...
Antti Mäntyniemi +2 more
semanticscholar +2 more sources
Arrayable TDC with Voltage-Controlled Ring Oscillator for dToF Image Sensors. [PDF]
As the resolution and conversion speed of time-to-digital conversion (TDC) chips continue to improve, the bit error rate also increases, leading to a decrease in the linearity of TDC and seriously affecting measurement accuracy.
Chen L, Li B, Cheng C.
europepmc +2 more sources
Time-to-digital converter (TDC) is the key technology to realize accurate time delay measurement in high-precision optical fiber time-frequency transmission and synchronization, optical sensing and many scientific applications.
Xiangyu Mao +5 more
doaj +2 more sources
A Scalable Sub-Picosecond TDC Based on Analog Sampling of Dual-Phase Signals from a Free-Running Oscillator. [PDF]
This work presents a novel time-to-digital converter based on the analog sampling of dual-phase periodic signals generated from a free-running oscillator.
Cardella R +9 more
europepmc +2 more sources

