Results 51 to 60 of about 15,872,036 (205)

Atomic Layer Deposition in Transistors and Monolithic 3D Integration

Advanced Functional Materials, Volume 36, Issue 41, 21 May 2026.
Transistors are fundamental building blocks of modern electronics. This review summarizes recent progress in atomic layer deposition (ALD) for the synthesis of two‐dimensional (2D) metal oxides and transition‐metal dichalcogenides (TMDCs), with particular emphasis on their enabling role in monolithic three‐dimensional (M3D) integration for next ...
Yue Liu, Taoyu Zou, Cheng‐Yan Xu, Liang Zhen, Yang Li, Yong‐Young Noh   +5 more
wiley   +1 more source

Emerging single‐element ferroelectrics: From theory to experiment

InfoMat, Volume 8, Issue 4, April 2026.
This review explores recent developments in single‐element ferroelectrics, covering mechanisms of ferroelectric behavior, their crystal structures, key preparation methods, ferroelectric performance characteristics, and promising device applications in field‐effect transistors, photodetectors, and visual perceptrons.
Run Zhao, Yuhang Zhang, Chen‐Min Dai, Fan Li, Jinlei Zhang, Ju Gao, Yucheng Jiang, Cheng‐Wei Qiu   +7 more
wiley   +1 more source

Sub-10-nm Asymmetric Junctionless Tunnel Field-Effect Transistors

IEEE Journal of the Electron Devices Society, 2014
This study presents a new asymmetric junctionless tunnel field-effect transistor (AJ-TFET) to scale TFETs into sub-10-nm regimes. The asymmetric junctionless p+ source/body and junctional n/p+ drain/body separately optimize the lateral source and drain ...
Chun-Hsing Shih, Nguyen Van Kien
doaj   +1 more source

Investigation of Single-Event-Transient Effects Induced by Heavy-Ion in All-Silicon DG-TFET

IEEE Access, 2022
The heavy-ion analysis is a single-event-effect (SEE) that produces a single-event-transient (SET) pulse of current. In this work, the analysis was done to observe the maximum impact of heavy-ions on a calibrated double-gate tunnel field-effect ...
Ashish Maurya, Kalyan Koley, Jitendra Kumar, Pankaj Kumar   +3 more
doaj   +1 more source

High‐Performance and Energy‐Efficient Sub‐5 nm 2D Double‐Gate MOSFETs Based on Silicon Arsenide Monolayers

Advanced Electronic Materials, Volume 12, Issue 5, 9 March 2026.
Sub‐5 nm double‐gate MOSFETs based on 2D SiAs monolayers are investigated using quantum transport simulations. By engineering source‐drain underlap regions, the devices achieve exceptional on‐currents of up to 1206 µA µm−1, surpassing the ITRS 2028 high‐performance targets.
Dogukan Hazar Ozbey, Engin Durgun
wiley   +1 more source

Low Power and Energy‐Efficient Design of MTJ/FinFET Circuits

Engineering Reports, Volume 8, Issue 3, March 2026.
This work begins by outlining the fundamental concepts of MTJs, FinFETs, and the conventional hybrid CMOS/MTJ framework. It then explains the operating mechanism and configuration of the proposed STT‐MTJ/FinFET‐based OR logic gate. The final sections present the simulation outcomes and analyze the influence of FinFET fin variation.
Pillem Ramesh, Atul S. M. Tripathi
wiley   +1 more source

Comparative Study of Steep Switching Devices for 1T Dynamic Memory

Tecnología en Marcha
This work focuses on understanding the operation and performance of various steep switching devices (subthreshold slope sub 60 mV/decade), namely Thin-Capacitively Coupled Thyristor (TCCT), Field Effect Diode (FED), Zero sub-threshold swing and Zero ...
Nupur Navlakha, Hasan Raza Ansari, Leonard Register, Sanjay Banerjee   +3 more
doaj   +1 more source

Electrostatically-Doped Hetero-Barrier Tunnel Field Effect Transistor: Design and Investigation

IEEE Access, 2018
In this paper, an electrostatically-doped hetero-barrier tunnel-field-effect-transistor (EDHet-TFET) based on stepped broken-gap (type-III) is simulated, investigated, and compared with the conventionally-doped stepped broken-gap hetero-barrier TFET (Het-
M. Ehteshamuddin, Abdullah G. Alharbi, Sajad A. Loan   +2 more
doaj   +1 more source

Design and TCAD Simulation of p+–n+ InAs‐Based TFET

Nano Select, Volume 7, Issue 3, March 2026.
A physics‐based design and optimization of a p+−n+${{p}^ + } - {{n}^ + }$ InAs tunnel field‐effect transistor is presented using calibrated quantum‐corrected TCAD simulations. By employing a composite figure of merit that unifies digital and RF metrics, the proposed homojunction architecture achieves steep subthreshold swing, enhanced cutoff frequency,
Muhammad Elgamal, Mona El Sabbagh, Fatma Shokry, Ahmed Shaker, Mohammed El‐Banna, Mohamed Abouelatta   +5 more
wiley   +1 more source

Computational design of two‐dimensional MA2Z4 family field‐effect transistor for future Ångström‐scale CMOS technology nodes

InfoMat, Volume 8, Issue 2, February 2026.
Two‐dimensional MA2Z4 such as MoSi2N4 offer a new path to extend transistor scaling beyond the limits of silicon. Due to their exceptional properties, these 2D semiconductors are promising candidates for future Ångström‐scale CMOS technology. This review outlines the computational design and roadmap bridging materials discovery, device design and ...
Che Chen Tho, Zongmeng Yang, Shibo Fang, Shiying Guo, Liemao Cao, Chit Siong Lau, Fei Liu, Shengli Zhang, Jing Lu, L. K. Ang, Lain‐Jong Li, Yee Sin Ang   +11 more
wiley   +1 more source