Results 81 to 90 of about 1,247 (195)
Small, Volume 21, Issue 30, July 29, 2025.This review categorizes ML‐TMDs into commensurate and incommensurate structures and examines their effects on electronic band structures, optical responses, ferroelectricity, and the anomalous Hall effect. It discusses synthetic methods, such as mechanical stacking, chemical vapor deposition (CVD), interfacial epitaxy, and hypotaxy, and introduces the ...
Hyun‐Geun Oh +7 more
wiley +1 more source
Advanced Electronic MaterialsCompact in‐memory computing architectures are desirable to embed artificial intelligence (AI) in resource‐restricted edge devices. However, current technologies face limitations in both the area and energy efficiency. Here, a reconfigurable ferroelectric
Zhongyunshen Zhu +2 more
doaj +1 more source
A New On-Chip ESD Strategy Using TFETs-TCAD Based Device and Network Simulations
IEEE Journal of the Electron Devices Society, 2018 For the first time, this paper reports the quasi-static behavior and the applicability of the tunnel field effect transistor (TFET) for the on-chip electrostatic discharge (ESD) protection. ESD evaluations are performed on 28-nm fully depleted silicon-on-
Radhakrishnan Sithanandam +1 more
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IEEE Journal of the Electron Devices Society, 2015 Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this paper, we: 1) review the perspectives of such devices for low-power high-frequency analog integrated circuit applications (e.g ...
Leonardo Barboni +2 more
doaj +1 more source
Miller effect suppression of tunnel field‐effect transistors (TFETs) using capacitor neutralisation
Electronics Letters, 2016 A novel method of suppressing the Miller effects of tunnel field‐effect transistors (TFETs) is proposed by using capacitor neutralisation. Since TFETs suffer from more severe Miller effects than metal‐oxide‐semiconductor FETs, conventional ways such as short‐gate structures are not sufficient to fully suppress the Miller effects of TFETs.
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DC ANALYSIS OF p-n-p-n TUNNELING FIELD-EFFECT TRANSISTOR BASED ON In0.35Ga0.65As
Holos, 2018 Using calibrated simulations, we report the In0.35Ga0.65As based tunnel field-effect transistor (TFET) with thin δ-doped n+ pocket at the source-channel interface to improve the parameters such as on current (Ion), off-current (Ioff) and subthreshold ...
Behnam Dorostkar, Saeid Marjani
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Random Dopant Fluctuation Effects of Tunneling Field-Effect Transistors (TFETs) [PDF]
Journal of the Institute of Electronics and Information Engineers, 2012 Jung-Shik Jang +2 more
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Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor [PDF]
Journal of Optoelectronical Nanostructures, 2019 In this paper, we have presented a heterojunction gate all around nanowiretunneling field effect transistor (GAA NW TFET) and have explained its characteristicsin details.
Mahsa Roohy, Reza Hosseini
doaj
IET Circuits, Devices and SystemsThis study explores the impact of integrating a gallium arsenide (GaAs) pocket at the source and drain in a dual-material gate-oxide-stack double-gate tunnel field-effect transistor (DMGOSDG-TFET).
Km. Sucheta Singh +4 more
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International Journal of Robotics and Automation TechnologyAbstract: Since, Dual Metal Gate (DMG) technology alone is not enough to rectify the problem of low ON current and large ambipolar current in the TFET, therefore, a novel TFET structure, known as dual metal triple-gate-dielectric (DM_TGD) TFET, has been proposed. We have combined the dielectric and gate material work function engineering to enhance the
Tan Chun Fui +2 more
openaire +2 more sources