Results 61 to 70 of about 2,562 (186)
, 2019 Due to the rigorous practice of scaling down the device technology, certain factors such as proper electrostatic controlling of the channel, dopingless substrate, and low thermal budget at the nanoscale are the keys to designing better, efficient and ...
Kumar, Naveen, Raman, Ashish
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A New Heterostructure Junctionless Tunnel Field Effect Transistor with Silicon-on-Nothing Technique for DC Parameter Improvement [PDF]
مجله مدل سازی در مهندسیIn this paper, a novel heterostructure junctionless tunnel field effect transistor with silicon-on-nothing technology (SON HS-JLTFET) is proposed. The proposed device has two advantages over conventional JLTFET.
Amin Vanak, Amir Amini
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Discover Nano, 2023 This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a triple metal gate (VTG-TFET). We obtained improved switching characteristics for the proposed design because of the improved electrostatic control on the channel
Dariush Madadi, Saeed Mohammadi
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Characterization of silicon tunnel field effect transistor based on charge plasma
, 2022 The aim of the proposed paper is an analytical model and realization of the characteristics for tunnel field-effect transistor (TFET) based on charge plasma (CP). One of the most applications of the TFET device which operates based on CP technique is the
Taha, Faris Hassan +1 more
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IET Circuits, Devices and Systems, 2023 In this article, a new p+ pocket stacked gate oxide junctionless tunnelling field effect transistor (junction less tunnelling field effect transistor (JLTFET)) which has metal strip in gate oxide layer is proposed for analogue/RF circuit applications ...
Alireza Zirak
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Improvement of Tunnel Field Effect Transistor Performance Using Auxiliary Gate and Retrograde Doping in the Channel [PDF]
Journal of Electrical and Computer Engineering Innovations, 2018 Background and Objectives: In this work, a dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor (DWG SP RD-TFET) is proposed and investigated.Methods: The dual workfunction gate-source pocket-retrograde doping-tunnel ...
M. Karbalaei, D. Dideban, N. Moezi
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Performance Projections for a Reconfigurable Tunnel NanoFET
IEEE Journal of the Electron Devices Society, 2017 Theoretical performance projections of a reconfigurable tunnel (RT) field-effect transistor (FET) employing multiple parallel 1-D channels are given. The RT-nanoFET can be reconfigured on demand from pto n-type and from low power (LP) to high performance
Stefan Blawid +3 more
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Si/Ge hetero-structure nanotube tunnel field effect transistor
, 2015 We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application.
A. N. Hanna +3 more
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Proposal of a p-type Back-Enhanced Tunnel Field Effect Transistor
, 2019 In this paper we propose a new p-type Tunnel Field Effect Transistor based on the planar Back-Enhanced structure (BE-pTFET), by removing the p-type drain doping and using a back bias to obtain similar on-state behaviors to those of a conventional pTFET ...
P. G. D. Agopian +5 more
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Effect of edge vacancies on performance of planar graphene tunnel field-effect transistor
, 2017 The influence of edge vacancies on the working ability of the planar graphene tunnel field-effect transistor (TFET) is studied at various concentrations and distributions (normal, uniform, periodic) of defects. All calculations are performed by using the
V. L. Katkov, A. A. Glebov, V. A. Osipov
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