Results 41 to 50 of about 342 (172)
Sub-10-nm Asymmetric Junctionless Tunnel Field-Effect Transistors
This study presents a new asymmetric junctionless tunnel field-effect transistor (AJ-TFET) to scale TFETs into sub-10-nm regimes. The asymmetric junctionless p+ source/body and junctional n/p+ drain/body separately optimize the lateral source and drain ...
Chun-Hsing Shih, Nguyen Van Kien
doaj +1 more source
Investigation of Single-Event-Transient Effects Induced by Heavy-Ion in All-Silicon DG-TFET
The heavy-ion analysis is a single-event-effect (SEE) that produces a single-event-transient (SET) pulse of current. In this work, the analysis was done to observe the maximum impact of heavy-ions on a calibrated double-gate tunnel field-effect ...
Ashish Maurya +3 more
doaj +1 more source
Emerging single‐element ferroelectrics: From theory to experiment
This review explores recent developments in single‐element ferroelectrics, covering mechanisms of ferroelectric behavior, their crystal structures, key preparation methods, ferroelectric performance characteristics, and promising device applications in field‐effect transistors, photodetectors, and visual perceptrons.
Run Zhao +7 more
wiley +1 more source
Sub‐5 nm double‐gate MOSFETs based on 2D SiAs monolayers are investigated using quantum transport simulations. By engineering source‐drain underlap regions, the devices achieve exceptional on‐currents of up to 1206 µA µm−1, surpassing the ITRS 2028 high‐performance targets.
Dogukan Hazar Ozbey, Engin Durgun
wiley +1 more source
High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor
A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel ...
Xiaoling Duan +6 more
doaj +1 more source
Low Power and Energy‐Efficient Design of MTJ/FinFET Circuits
This work begins by outlining the fundamental concepts of MTJs, FinFETs, and the conventional hybrid CMOS/MTJ framework. It then explains the operating mechanism and configuration of the proposed STT‐MTJ/FinFET‐based OR logic gate. The final sections present the simulation outcomes and analyze the influence of FinFET fin variation.
Pillem Ramesh, Atul S. M. Tripathi
wiley +1 more source
Comparative Study of Steep Switching Devices for 1T Dynamic Memory
This work focuses on understanding the operation and performance of various steep switching devices (subthreshold slope sub 60 mV/decade), namely Thin-Capacitively Coupled Thyristor (TCCT), Field Effect Diode (FED), Zero sub-threshold swing and Zero ...
Nupur Navlakha +3 more
doaj +1 more source
Design and TCAD Simulation of p+–n+ InAs‐Based TFET
A physics‐based design and optimization of a p+−n+${{p}^ + } - {{n}^ + }$ InAs tunnel field‐effect transistor is presented using calibrated quantum‐corrected TCAD simulations. By employing a composite figure of merit that unifies digital and RF metrics, the proposed homojunction architecture achieves steep subthreshold swing, enhanced cutoff frequency,
Muhammad Elgamal +5 more
wiley +1 more source
L-shaped tunnel field-effect transistor (TFET) provides higher on-current than a conventional TFET through band-to-band tunneling in the vertical direction of the channel.
Junsu Yu +7 more
doaj +1 more source
Two‐dimensional MA2Z4 such as MoSi2N4 offer a new path to extend transistor scaling beyond the limits of silicon. Due to their exceptional properties, these 2D semiconductors are promising candidates for future Ångström‐scale CMOS technology. This review outlines the computational design and roadmap bridging materials discovery, device design and ...
Che Chen Tho +11 more
wiley +1 more source

