Results 91 to 100 of about 12,217,467 (150)

Spatial Charge Trap Engineering with Boron Nitride Barrier for 3D V-NAND Flash Memory

Spatial charge trap engineering using amorphous boron nitride (BN) energy barrier for 3D V-NAND flash memory device is presented. A 1 nm thick BN layer is inserted within a silicon nitride (SiN) charge trap layer (CTL) using an In-situ ALD process.
Kang, Daehyun, Cho, Byung-Jin, Jeong, Jae Joong, Sin, Dong Hun, Park, Young Keun, Choi, Han Mei   +5 more
core   +1 more source

Physical Unclonable Function Based on 3D-NAND Flash Array Structure With Multi-Chip Implementation. [PDF]

Small
Hwang H, Youn S, Park J, Yu D, Kim H.
europepmc   +1 more source

Capacitive in-memory vector-matrix multiplication computing with charge-trap memcapacitors. [PDF]

Nano Converg
Yu J, Hwang H, Kim H, Choi WY.
europepmc   +1 more source

PosFFS2 : A New NAND Flash Memory File System Supporting Snapshot In Embedded Linux

, 2010
MasterFlash memory is widely used as a storage device for mobile devices because of its lightweight and non-volatility. Flash memory comes in two favors: NOR and NAND. NOR is byte-addressable and designed for code storage.
오용석
core  

Residual stress modulation as a pathway to reliable multilevel 3D NAND flash storage. [PDF]

Nanoscale Adv
Zhou R, Kim IJ, Park S, Kwon H, Lee JS.
europepmc   +1 more source

Incremental Pulse-Width Erase (IPWE) Scheme for Fast and Variation-Tolerant GIDL Erase of 3D NAND Flash. [PDF]

Micromachines (Basel)
Park Y, Shim W.
europepmc   +1 more source

Effects of Edge Thinning on Fowler-Nordheim Tunneling Current of NAND-Type Flash Memory Cells

, 2011
The edge thinning of tunnel oxide is numerically found to increase the Fowler-Nordheim (FN) tunneling gate current in NAND-type Flash cells during programming and erasing operations.
Ji-Ting Liang, Yan-Xiang Luo, Wen-Fa Wu, Chun-Hsing Shih, Nguyễn, Đăng Chiến, Ruei-Kai Shia, Chenhsin Lien, Sau-Mou Wu, Ming-Kun Huang   +8 more
core  

Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack. [PDF]

Nano Lett
Fernandes L, Wodzro S, Venkatesan P, Ravikumar P, Lee MY, Shon M, Chakraborty D, Song T, Kang S, Soliman S, Tian M, Yeager J, Adler J, Chen J, Wang Z, Wolfe D, Yu S, Padovani A, Datta S, Ray B, Khan A.   +20 more
europepmc   +1 more source

TiO₂ nanolayer-assisted top-interface engineering for disturbance-free FeFETs: a blueprint for future van der Waals memory. [PDF]

Nano Converg
Kang H, Kwak J, Kim G, Lee S, Kim Y, Park S, Lim S, Seo K, Kim W, Ha D, Ahn J, Jeon S.   +11 more
europepmc   +1 more source

Enhanced programming efficiency in vertical NAND flash using self-boosting hot carrier injection. [PDF]

Sci Rep
Kim M, Hong J, Kim C, Kim SJ, Hwang S, Baik SJ, Jeon J.   +6 more
europepmc   +1 more source